Unify & feature gate Xtensa asm

[MabezDev]

This is a WIP fleshing out of an idea we discussed a few meetings back, using the CPU features to manipulate what code is generated. As it stands, there is support for conditionally compiling {save|restore}_context, along with the Context structure. It should hopefully close #26.

It should hopefully be possible to remove the lx106 specific code (for the esp8266), but this might be a bit more tricky; see below.

Questions

• How to handle the vector table & exception handlers?
  • The number will vary depending on the silicon.
  • Is there ISA defined ordering of the vector table, i.e Will DebugExceptionVector always come before NMIExceptionVector or is this how Espressif chose to layout the table in their chips?
• How to handle features (internal timers, interrupt levels, etc) that are not possible to find from the CPU features?

cc: @jessebraham @igrr