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esp32c6-lp-hal package (#714)
* Create the `esp32c6-lp-hal` package * Update CHANGELOG
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| [target.riscv32imac-unknown-none-elf] | ||
| runner = "espflash flash --monitor" | ||
| rustflags = [ | ||
| "-C", "link-arg=-Tlinkall.x", | ||
| ] | ||
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| [build] | ||
| target = "riscv32imac-unknown-none-elf" | ||
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| [unstable] | ||
| build-std = ["core"] |
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| [package] | ||
| name = "esp32c6-lp-hal" | ||
| version = "0.1.0" | ||
| edition = "2021" | ||
| rust-version = "1.65.0" | ||
| description = "HAL for ESP32-C6's low-power coprocessor" | ||
| repository = "https://github.com/esp-rs/esp-hal" | ||
| license = "MIT OR Apache-2.0" | ||
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| keywords = [ | ||
| "embedded", | ||
| "embedded-hal", | ||
| "esp", | ||
| "esp32c6", | ||
| "no-std", | ||
| ] | ||
| categories = [ | ||
| "embedded", | ||
| "hardware-support", | ||
| "no-std", | ||
| ] | ||
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| [dependencies] | ||
| critical-section = { version = "1.1.2", features = ["restore-state-u8"] } | ||
| embedded-hal = { version = "0.2.7", features = ["unproven"] } | ||
| esp32c6-lp = { git = "https://github.com/esp-rs/esp-pacs", rev = "a9cad5e", features = ["critical-section"] } | ||
| riscv = "0.10.1" | ||
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| [features] | ||
| default = [] | ||
| debug = ["esp32c6-lp/impl-register-debug"] |
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| # esp32c6-lp-hal | ||
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| [](https://crates.io/crates/esp32c6-lp-hal) | ||
| [](https://docs.rs/esp32c6-lp-hal) | ||
|  | ||
| [](https://matrix.to/#/#esp-rs:matrix.org) | ||
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| `no_std` HAL for the ESP32-C6 from Espressif's low-power coprocessor. Implements a number of the traits defined by [embedded-hal](https://github.com/rust-embedded/embedded-hal). | ||
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| This device uses the RISC-V ISA, which is officially supported by the Rust compiler via the `riscv32imac-unknown-none-elf` target. Refer to the [Getting Started](#getting-started) section below for more information. | ||
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| ## [Documentation] | ||
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| [documentation]: https://docs.rs/esp32c6-lp-hal/ | ||
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| ## Getting Started | ||
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| ### Installing the Rust Compiler Target | ||
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| The compilation target for this device is officially supported via the `stable` release channel and can be installed via [rustup](https://rustup.rs/): | ||
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| ```shell | ||
| $ rustup target add riscv32imac-unknown-none-elf | ||
| ``` | ||
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| ## License | ||
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| Licensed under either of: | ||
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| - Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) | ||
| - MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT) | ||
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| at your option. | ||
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| ### Contribution | ||
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| Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in | ||
| the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without | ||
| any additional terms or conditions. |
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| use std::{env, fs::File, io::Write, path::PathBuf}; | ||
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| fn main() { | ||
| // Put the linker script somewhere the linker can find it | ||
| let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); | ||
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| File::create(out.join("link.x")) | ||
| .unwrap() | ||
| .write_all(include_bytes!("ld/link.x")) | ||
| .unwrap(); | ||
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| println!("cargo:rustc-link-search={}", out.display()); | ||
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| // Only re-run the build script when memory.x is changed, | ||
| // instead of when any part of the source code changes. | ||
| println!("cargo:rerun-if-changed=ld/memory.x"); | ||
| } |
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| /* | ||
| * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| ENTRY(reset_vector) | ||
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| CONFIG_ULP_COPROC_RESERVE_MEM = 1024 * 16; | ||
| CONFIG_ULP_SHARED_MEM = 0; | ||
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| MEMORY | ||
| { | ||
| /*first 128byte for exception/interrupt vectors*/ | ||
| vector_table(RX) : ORIGIN = 0x50000000, LENGTH = 0x80 | ||
| ram(RWX) : ORIGIN = 0x50000080, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - 0x80 - CONFIG_ULP_SHARED_MEM | ||
| } | ||
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| SECTIONS | ||
| { | ||
| .vector.text : | ||
| { | ||
| /*exception/interrupt vectors*/ | ||
| __mtvec_base = .; | ||
| KEEP (*(.init.vector)) | ||
| __mtvec_end = .; | ||
| } > vector_table | ||
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| . = ORIGIN(ram); | ||
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| .text ALIGN(4): | ||
| { | ||
| *(.text.vectors) /* Default reset vector must link to offset 0x80 */ | ||
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| KEEP(*(.init)); | ||
| KEEP(*(.init.rust)); | ||
| *(.text) | ||
| *(.text*) | ||
| } > ram | ||
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| .rodata ALIGN(4): | ||
| { | ||
| *(.rodata) | ||
| *(.rodata*) | ||
| } > ram | ||
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| .data ALIGN(4): | ||
| { | ||
| *(.data) | ||
| *(.data*) | ||
| *(.sdata) | ||
| *(.sdata*) | ||
| } > ram | ||
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| .bss ALIGN(4) : | ||
| { | ||
| *(.bss) | ||
| *(.bss*) | ||
| *(.sbss) | ||
| *(.sbss*) | ||
| PROVIDE(end = .); | ||
| } > ram | ||
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| __stack_top = ORIGIN(ram) + LENGTH(ram); | ||
| } |
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