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soc/interconnect/wishbone: Move burst cycles support option to SoCBus…
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…Handler/SoC classes
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@koluckirafal
koluckirafal committed Apr 6, 2022
1 parent 0cfed61 commit e8ce171
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Showing 4 changed files with 31 additions and 29 deletions.
15 changes: 10 additions & 5 deletions litex/soc/integration/soc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,7 @@ class SoCBusHandler(Module):
supported_address_width = [32]

# Creation -------------------------------------------------------------------------------------
def __init__(self, name="SoCBusHandler", standard="wishbone", data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
def __init__(self, name="SoCBusHandler", standard="wishbone", data_width=32, address_width=32, timeout=1e6, bursting=False, reserved_regions={}):
self.logger = logging.getLogger(name)
self.logger.info("Creating Bus Handler...")

Expand Down Expand Up @@ -149,6 +149,7 @@ def __init__(self, name="SoCBusHandler", standard="wishbone", data_width=32, add
self.standard = standard
self.data_width = data_width
self.address_width = address_width
self.bursting = bursting
self.masters = {}
self.slaves = {}
self.regions = {}
Expand Down Expand Up @@ -719,6 +720,7 @@ def __init__(self, platform, sys_clk_freq,
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = 1e6,
bus_bursting = False,
bus_reserved_regions = {},

csr_data_width = 32,
Expand Down Expand Up @@ -756,6 +758,7 @@ def __init__(self, platform, sys_clk_freq,
data_width = bus_data_width,
address_width = bus_address_width,
timeout = bus_timeout,
bursting = bus_bursting,
reserved_regions = bus_reserved_regions,
)

Expand Down Expand Up @@ -837,7 +840,7 @@ def add_controller(self, name="ctrl", **kwargs):
colorer("added", color="green")))
setattr(self.submodules, name, SoCController(**kwargs))

def add_ram(self, name, origin, size, contents=[], mode="rw", burst=False):
def add_ram(self, name, origin, size, contents=[], mode="rw"):
ram_cls = {
"wishbone": wishbone.SRAM,
"axi-lite": axi.AXILiteSRAM,
Expand All @@ -847,7 +850,7 @@ def add_ram(self, name, origin, size, contents=[], mode="rw", burst=False):
"axi-lite": axi.AXILiteInterface,
}[self.bus.standard]
ram_bus = interface_cls(data_width=self.bus.data_width)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), burst=burst)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
Expand All @@ -858,8 +861,8 @@ def add_ram(self, name, origin, size, contents=[], mode="rw", burst=False):
if contents != []:
self.add_config(f"{name}_INIT", 1)

def add_rom(self, name, origin, size, contents=[], mode="r", burst=False):
self.add_ram(name, origin, size, contents, mode=mode, burst=burst)
def add_rom(self, name, origin, size, contents=[], mode="r"):
self.add_ram(name, origin, size, contents, mode=mode)

def init_rom(self, name, contents=[], auto_size=True):
self.logger.info("Initializing ROM {} with contents (Size: {}).".format(
Expand Down Expand Up @@ -991,6 +994,7 @@ def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=N
standard = "wishbone",
data_width = self.bus.data_width,
address_width = self.bus.address_width,
bursting = self.bus.bursting
)
dma_bus = wishbone.Interface(data_width=self.bus.data_width)
self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
Expand Down Expand Up @@ -1078,6 +1082,7 @@ def do_finalize(self):
self.add_constant("CONFIG_BUS_STANDARD", self.bus.standard.upper())
self.add_constant("CONFIG_BUS_DATA_WIDTH", self.bus.data_width)
self.add_constant("CONFIG_BUS_ADDRESS_WIDTH", self.bus.address_width)
self.add_constant("CONFIG_BUS_BURSTING", int(self.bus.bursting))

# SoC DMA Bus Interconnect (Cache Coherence) -----------------------------------------------
if hasattr(self, "dma_bus"):
Expand Down
23 changes: 9 additions & 14 deletions litex/soc/integration/soc_core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ def __init__(self, platform, clk_freq,
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = 1e6,
bus_bursting = False,

# CPU parameters
cpu_type = "vexriscv",
Expand All @@ -78,17 +79,14 @@ def __init__(self, platform, clk_freq,
integrated_rom_size = 0,
integrated_rom_mode = "r",
integrated_rom_init = [],
integrated_rom_burst = False,

# SRAM parameters
integrated_sram_size = 0x2000,
integrated_sram_init = [],
integrated_sram_burst = False,

# MAIN_RAM parameters
integrated_main_ram_size = 0,
integrated_main_ram_init = [],
integrated_main_ram_burst = False,
integrated_main_ram_size = 0,
integrated_main_ram_init = [],

# CSR parameters
csr_data_width = 32,
Expand Down Expand Up @@ -125,6 +123,7 @@ def __init__(self, platform, clk_freq,
bus_data_width = bus_data_width,
bus_address_width = bus_address_width,
bus_timeout = bus_timeout,
bus_bursting = bus_bursting,
bus_reserved_regions = {},

csr_data_width = csr_data_width,
Expand Down Expand Up @@ -201,16 +200,14 @@ def __init__(self, platform, clk_freq,
origin = self.cpu.reset_address,
size = integrated_rom_size,
contents = integrated_rom_init,
mode = integrated_rom_mode,
burst = integrated_rom_burst
mode = integrated_rom_mode
)

# Add integrated SRAM
if integrated_sram_size:
self.add_ram("sram",
origin = self.mem_map["sram"],
size = integrated_sram_size,
burst = integrated_sram_burst
)

# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
Expand All @@ -219,7 +216,6 @@ def __init__(self, platform, clk_freq,
origin = self.mem_map["main_ram"],
size = integrated_main_ram_size,
contents = integrated_main_ram_init,
burst = integrated_main_ram_burst,
)

# Add Identifier
Expand Down Expand Up @@ -307,6 +303,7 @@ def soc_core_args(parser):
soc_group.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width.")
soc_group.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width.")
soc_group.add_argument("--bus-timeout", default=int(1e6), type=float, help="Bus timeout in cycles.")
soc_group.add_argument("--bus-bursting", action="store_true", help="Enable burst cycles on the bus if supported.")

# CPU parameters
soc_group.add_argument("--cpu-type", default="vexriscv", help="Select CPU: {}.".format(", ".join(iter(cpu.CPUS.keys()))))
Expand All @@ -318,13 +315,11 @@ def soc_core_args(parser):
soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.")

# ROM parameters
soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).")
soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")
soc_group.add_argument("--integrated-rom-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).")
soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).")
soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")

# SRAM parameters
soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.")
soc_group.add_argument("--integrated-sram-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).")
soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.")

# MAIN_RAM parameters
soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.")
Expand Down
5 changes: 3 additions & 2 deletions litex/soc/interconnect/axi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -182,10 +182,11 @@ def r_lite_description(data_width):
]

class AXILiteInterface:
def __init__(self, data_width=32, address_width=32, clock_domain="sys", name=None):
def __init__(self, data_width=32, address_width=32, clock_domain="sys", name=None, bursting=False):
self.data_width = data_width
self.address_width = address_width
self.clock_domain = clock_domain
self.bursting = False # Not supported in AXI Lite

self.aw = stream.Endpoint(ax_lite_description(address_width), name=name)
self.w = stream.Endpoint(w_lite_description(data_width), name=name)
Expand Down Expand Up @@ -783,7 +784,7 @@ def __init__(self, axi_lite=None, bus_csr=None, register=False):
# AXILite SRAM -------------------------------------------------------------------------------------

class AXILiteSRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
if bus is None:
bus = AXILiteInterface()
self.bus = bus
Expand Down
17 changes: 9 additions & 8 deletions litex/soc/interconnect/wishbone.py
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Original file line number Diff line number Diff line change
Expand Up @@ -41,9 +41,10 @@


class Interface(Record):
def __init__(self, data_width=32, adr_width=30):
self.data_width = data_width
self.adr_width = adr_width
def __init__(self, data_width=32, adr_width=30, bursting=False):
self.data_width = data_width
self.adr_width = adr_width
self.bursting = bursting
Record.__init__(self, set_layout_parameters(_layout,
adr_width = adr_width,
data_width = data_width,
Expand Down Expand Up @@ -330,7 +331,7 @@ def __init__(self, master, slave):
# Wishbone SRAM ------------------------------------------------------------------------------------

class SRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
if bus is None:
bus = Interface()
self.bus = bus
Expand All @@ -348,7 +349,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False
read_only = False

###
if burst:
if self.bus.bursting:
adr_wrap_mask = Array((0b0000, 0b0011, 0b0111, 0b1111))
adr_wrap_max = adr_wrap_mask[-1].bit_length()

Expand Down Expand Up @@ -431,7 +432,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False
self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
for i in range(bus_data_width//8)]
# address and data
if burst:
if self.bus.bursting:
self.comb += [
If(adr_burst & adr_latched,
port.adr.eq(adr_next[:len(port.adr)]),
Expand All @@ -448,12 +449,12 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False
]
if not read_only:
self.comb += port.dat_w.eq(self.bus.dat_w),

# generate ack
self.sync += [
self.bus.ack.eq(0)
]
if burst:
if self.bus.bursting:
self.sync += [
If(self.bus.cyc & self.bus.stb & (~self.bus.ack | adr_burst), self.bus.ack.eq(1))
]
Expand Down

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