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Add newfill cell to cvc pdk #140

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Add newfill cell to cvc pdk #140

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fa3009b
Add cell newfill_12 to pdk
M0stafaRady Nov 26, 2024
3a83a9d
remove celldefine from scan chain ff to backaccess them in simualtion
M0stafaRady Nov 26, 2024
e2dd5e3
Revert "remove celldefine from scan chain ff to backaccess them in si…
M0stafaRady Dec 4, 2024
b3aff8f
Add cell sky130_ef_sc_hd__fill_12
M0stafaRady Dec 18, 2024
cfb7c1e
remove sky130_ef_sc_hd__newfill_12 and add sky130_ef_sc_hd__fill_2, …
M0stafaRady Jan 21, 2025
e55e9c2
revert removing sky130_ef_sc_hd__fill_12 again
M0stafaRady Jan 21, 2025
6b9d8e7
fix endif position
M0stafaRady Jan 21, 2025
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290 changes: 289 additions & 1 deletion verilog/cvc-pdk/sky130_fd_sc_hd.v
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Original file line number Diff line number Diff line change
Expand Up @@ -127875,5 +127875,293 @@ endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_4_V

`ifdef USE_POWER_PINS
/*********************************************************/

//--------EOF---------
`celldefine
module sky130_ef_sc_hd__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);

// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_ef_sc_hd__fill_2 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_ef_sc_hd__decap_20_12 (
VPWR,
VGND,
VPB ,
VNB
);

// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`ifdef FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_20_12 ();
// No contents.
endmodule
`endcelldefine

`else // If not FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_20_12 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine

`endif // If not FUNCTIONAL

/*********************************************************/
`endif // If not USE_POWER_PINS


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_ef_sc_hd__decap_40_12 (
VPWR,
VGND,
VPB ,
VNB
);

// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`ifdef FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_40_12 ();
// No contents.
endmodule
`endcelldefine

`else // If not FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_40_12 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine

`endif // If not FUNCTIONAL

/*********************************************************/
`endif // If not USE_POWER_PINS

`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_ef_sc_hd__decap_60_12 (
VPWR,
VGND,
VPB ,
VNB
);

// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`ifdef FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_60_12 ();
// No contents.
endmodule
`endcelldefine

`else // If not FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_60_12 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine

`endif // If not FUNCTIONAL



/*********************************************************/
`endif // If not USE_POWER_PINS



`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_ef_sc_hd__decap_80_12 (
VPWR,
VGND,
VPB ,
VNB
);

// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`ifdef FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_80_12 ();
// No contents.
endmodule
`endcelldefine

`else // If not FUNCTIONAL

`celldefine
module sky130_ef_sc_hd__decap_80_12 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine

`endif // If not FUNCTIONAL
/*********************************************************/
`endif // If not USE_POWER_PINS

`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine



module sky130_ef_sc_hd__fill_12 (
VPWR,
VGND,
VPB ,
VNB
);

input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_ef_sc_hd__fill_12 ();

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine


/*********************************************************/
`endif // USE_POWER_PINS


//--------EOF---------`