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Add cell newfill_12 to pdk
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M0stafaRady committed Nov 26, 2024
1 parent 503eda0 commit fa3009b
Showing 1 changed file with 25 additions and 1 deletion.
26 changes: 25 additions & 1 deletion verilog/cvc-pdk/sky130_fd_sc_hd.v
Original file line number Diff line number Diff line change
Expand Up @@ -127875,5 +127875,29 @@ endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_4_V

`ifdef USE_POWER_PINS

//--------EOF---------
`celldefine
module sky130_ef_sc_hd__newfill_12 (
VPWR,
VGND,
VPB ,
VNB
);

input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`else // USE_POWER_PINS
`celldefine
module sky130_ef_sc_hd__newfill_12 ();
// No contents.
endmodule
`endcelldefine
`endif // USE_POWER_PINS

//--------EOF---------`

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