Updating vcs netlists to include caravan

verilog/includes/gl_caravel_vcs.list

@@ -62,16 +62,20 @@
 -v $CARAVEL_PATH/rtl/debug_regs.v
 -v $CARAVEL_PATH/rtl/__user_project_la_example.v
 -v $CARAVEL_PATH/rtl/__user_project_gpio_example.v
--v $CARAVEL_PATH/rtl/__user_project_wrapper.v	     
+#-v $CARAVEL_PATH/rtl/__user_project_wrapper.v	     
+#-v $CARAVEL_PATH/rtl/__user_analog_project_wrapper.v	     
 -v $CARAVEL_PATH/gl/user_id_programming.v	     
 -v $CARAVEL_PATH/gl/caravel.v 		     
+-v $CARAVEL_PATH/gl/caravan.v 		     
 -v $CARAVEL_PATH/gl/buff_flash_clkrst.v 		     
 -v $CARAVEL_PATH/gl/gpio_signal_buffering.v 		     
+-v $CARAVEL_PATH/gl/gpio_signal_buffering_alt.v	     
 
 ###########################################################
 ## These blocks are manually designed 		
 ###########################################################
 -v $CARAVEL_PATH/gl/constant_block.v
+-v $CARAVEL_PATH/gl/chip_io_alt.v 
 -v $CARAVEL_PATH/gl/chip_io.v 
 -v $CARAVEL_PATH/gl/mgmt_protect.v		     
 -v $CARAVEL_PATH/gl/mgmt_protect_hv.v 	     		     

verilog/includes/rtl_caravel_vcs.v

@@ -52,9 +52,14 @@
 `ifdef GPIO_TESTING
 `include "caravel/verilog/rtl/__user_project_gpio_example.v"
 `endif
-`include "caravel/verilog/rtl/__user_project_wrapper.v"
+// `ifndef CARAVAN
+// `include "caravel/verilog/rtl/__user_project_wrapper.v"
+// `else
+// `include "caravel/verilog/rtl/__user_analog_project_wrapper.v"
+// `endif
 `include "caravel/verilog/rtl/user_id_programming.v"	     
 `include "caravel/verilog/rtl/caravel.v" 		     
+`include "caravel/verilog/rtl/caravan.v" 		     
 
 // These blocks are manually designed 		
 `include "caravel/verilog/gl/gpio_defaults_block_0403.v"