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fix conflicts (update license)
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NouranAbdelaziz committed Jan 13, 2025
2 parents d4bccb2 + 60e42c8 commit 6c2a4fd
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6 changes: 6 additions & 0 deletions EF_QSPI_XIP_CTRL.yaml
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Expand Up @@ -20,11 +20,13 @@ info:
type": soft
status: verified
cell_count:
- IP: 1973
- AHBL: 1973
width": "0.0"
height": "0.0"
technology: n/a
clock_freq_mhz:
- IP: 250
- AHBL: 250
digital_supply_voltage: n/a
analog_supply_voltage: n/a
Expand All @@ -40,6 +42,10 @@ parameters:
default: 999
description: The number of cycles needed for the s/w reset command; reset time = (RESET_CYCLES + 1) * 2 /(HCLK frequency).

clock:
name: clk
gated: 'no'

external_interface:
- name: sck
direction: output
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70 changes: 39 additions & 31 deletions README.md
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@@ -1,27 +1,12 @@
# EF_QSPI_XIP_CTRL
Quad I/O SPI Flash memory controller with support for:
- AHB lite interface
- Execute in Place (XiP)
- Nx16 Direct-Mapped Cache (default: N=32).

Intended to be used with SoCs that have no on-chip flash memory.


## Performance
The following data is obtained using Sky130 HD library
| Configuration | # of Cells (K) | Delay (ns) | I<sub>dyn</sub> (mA/MHz) | I<sub>s</sub> (nA) |
|---------------|----------------|------------|--------------------------|--------------------|
| 16x16 | 7.2 | 12 | 0.0625 | 20 |
| 32x16 | 14.3 | 17 | 0.126 | 39.5 |


AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP.
A QSPI XiP Flash COntroller with a parameterized Direct-Mapped Cache.
## The wrapped IP


The IP comes with an AHBL Wrapper

### Wrapped IP System Integration
#### Wrapped IP System Integration

```verilog
EF_QSPI_XIP_CTRL_AHBL INST (
Expand All @@ -48,22 +33,49 @@ EF_QSPI_XIP_CTRL_AHBL INST (
The following table is the result for implementing the EF_QSPI_XIP_CTRL IP with different wrappers using Sky130 PDK and [OpenLane2](https://github.com/efabless/openlane2) flow.
|Module | Number of cells | Max. freq |
|---|---|---|
|EF_QSPI_XIP_CTRL|534| 384 MHz |
|EF_QSPI_XIP_CTRL_AHBL|13024|40 MHz|
|EF_QSPI_XIP_CTRL|1973| 250 |
|EF_QSPI_XIP_CTRL_AHBL|1973|250|
## The Programmer's Interface


### Registers

|Name|Offset|Reset Value|Access Mode|Description|
|---|---|---|---|---|

### Clock Gating
The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the ``GCLK`` register. This capability is implemented through the ``ef_util_gating_cell`` module, which is part of the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the ``CLKG_GENERIC`` macro. Alternatively, define the ``CLKG_SKY130_HD`` macro if you wish to use the SKY130 HD library clock gating cell, ``sky130_fd_sc_hd__dlclkp_4``.

**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to enable the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update OpenLane2 YAML configuration file as follows:
```
VERILOG_DEFINES:
- CLKG_SKY130_HD
```

### The Interface
<img src="docs/EF_QSPI_XIP_CTRL.svg" width="600"/>

<img src="docs/_static/EF_QSPI_XIP_CTRL.svg" width="600"/>

#### Module Parameters

|Parameter|Description|Default Value|
|---|---|---|
|NUM_LINES|The cache number of lines.|16|
|LINE_SIZE|The cache line size in bytes.|32|
|RESET_CYCLES|The number of cycles needed for the s/w reset command; reset time = (RESET_CYCLES + 1) * 2 /(HCLK frequency).|999|

#### Ports

|Port|Direction|Width|Description|
|---|---|---|---|
|sck|output|1|spi serial clock|
|ce_n|output|1|slave select signal|
|din|input|4|spi data in|
|dout|output|4|spi data out|
|douten|output|4|spi data out enable|

|sck|output|1|SPI serial clock|
|ce_n|output|1|SPI chip select (Active Low).|
|dout|output|4|Flash controller SPI data out.|
|din|input|4|Flash controller SPI data in.|
|douten|output|4|Flash controller data out enable (Active Low)|
## Firmware Drivers:
Firmware drivers for EF_QSPI_XIP_CTRL can be found in the [fw](https://github.com/efabless/EF_QSPI_XIP_CTRL/tree/main/fw) directory. EF_QSPI_XIP_CTRL driver documentation is available [here](https://github.com/efabless/EF_QSPI_XIP_CTRL/blob/main/fw/README.md).
You can also find an example C application using the EF_QSPI_XIP_CTRL drivers [here]().
## Installation:
You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM).
##### 1. Using [IPM](https://github.com/efabless/IPM):
Expand All @@ -74,8 +86,4 @@ You can install the IP either by cloning this repository or by using [IPM](https
- Clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, which includes the required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v).
```git clone https://github.com/efabless/EF_IP_UTIL.git```
- Clone the IP repository
```git clone https://github.com/efabless/EF_QSPI_XIP_CTRL.git```

## Todo:
- [ ] support for WB bus
- [ ] Support cache configurations other than 16 bytes per line
```git clone github.com/efabless/EF_QSPI_XIP_CTRL```
1 change: 0 additions & 1 deletion hdl/rtl/DMC.v
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Expand Up @@ -16,7 +16,6 @@
limitations under the License.
*/

`timescale 1ns/1ps
`default_nettype none

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1 change: 0 additions & 1 deletion hdl/rtl/EF_QSPI_XIP_CTRL.v
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Expand Up @@ -16,7 +16,6 @@
limitations under the License.
*/

`timescale 1ns/1ps
`default_nettype none

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1 change: 1 addition & 0 deletions hdl/rtl/bus_wrappers/EF_QSPI_XIP_CTRL_AHBL.v
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Expand Up @@ -16,6 +16,7 @@
limitations under the License.
*/

`timescale 1ns/1ps
`default_nettype none

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75 changes: 75 additions & 0 deletions ipm_package.bash
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@@ -0,0 +1,75 @@
#!/bin/bash
# to run use bash ipm_package.bash --version x.x.x --ip_name name
# More safety, by turning some bugs into errors.
set -o errexit -o pipefail -o nounset

# now enjoy the options in order and nicely split until we see --
# option --output/-o requires 1 argument
LONGOPTS=version:ip_name:
OPTIONS=

# -temporarily store output to be able to check for errors
# -activate quoting/enhanced mode (e.g. by writing out "--options")
# -pass arguments only via -- "$@" to separate them correctly
# -if getopt fails, it complains itself to stdout
PARSED=$(getopt --options=$OPTIONS --longoptions=$LONGOPTS --name "$0" -- "$@") || exit 2
# read getopt's output this way to handle the quoting right:
eval set -- "$PARSED"
unset PARSED


while true; do
case "$1" in
--version)
version="$2"
shift 2
;;
--)
--ip_name)
ip_name="$2"
shift 2
;;
--)
shift
break
;;
*)
echo "Programming error"
exit 3
;;
esac
done

echo "+ version=$version"

# zip needed files


tar czf v$version.tar.gz --files-from <(find . | grep -v "\./verify" | grep -v "\./fw/Doxyfile" | grep -v "\./ipm_package.bash" | grep -v ".*\.dev\.v" | grep -v "\./hdl/rtl/bus_wrappers/dft" | grep -v "\.git" | grep -v "\.tar\.gz" | grep -v "\./ip" | grep -v "\./docs" | grep -v "\.\$"; ls "./ip/dependencies.json")
# tar czf v$version.tar.gz \
# --exclude='verify' \
# --exclude='hdl/rtl/bus_wrappers/dft' \
# --exclude='hdl/rtl/bus_wrappers/*.dev.v' \
# --exclude='ipm_package.bash' \
# --exclude='fw/Doxyfile' \
# --include='*.c' \
# *
# get checksum
shasum -a 256 v$version.tar.gz > v$version.tar.gz.sha256

# update yaml
sed -i "s/version.*/version: v$version/" *.yaml
sed -i "s/date.*/date: $(date +"%Y-%m-%d")/" *.yaml

# create tag
git tag -a $ip_name-v$version -m "Release version $version"
git push origin $ip_name-v$version

# create release
set -x
if gh release view $ip_name-v$version > /dev/null 2>&1; then
echo "Release $ip_name-v$version already exists. Skipping..."
else
echo "Creating release $ip_name-v$version..."
gh release create $ip_name-v$version v$version.tar.gz -t "$ip_name-v$version" --notes "sha256: $(cat v$version.tar.gz.sha256)"
fi
2 changes: 1 addition & 1 deletion verify/uvm-python/top.v
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Expand Up @@ -22,7 +22,7 @@ module top();
wire [3:0] dout;
wire [3:0] douten;
// design
EF_QSPI_XIP_CTRL_ahbl dut(
EF_QSPI_XIP_CTRL_AHBL dut(
.HCLK(CLK),
.HRESETn(RESETn),
.HADDR(HADDR),
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