include clock gate sky 130 cell inside ifdef block for fpga implmenta…

…tion
efabless · Sep 17, 2024 · 1906a32 · 1906a32
1 parent 7172bcb
commit 1906a32
Show file tree

Hide file tree

Showing 3 changed files with 36 additions and 28 deletions.
diff --git a/EF_I2C.yaml b/EF_I2C.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.12
-  date: 27-08-2024
+  version: v1.0.13
+  date: 17-09-2024
   category: digital
   tags:
   - peripheral

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v
@@ -79,19 +79,23 @@ module EF_I2C_APB # (
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
 
-    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-    `ifdef USE_POWER_PINS 
-        .VPWR(VPWR), 
-        .VGND(VGND), 
-        .VNB(VGND),
-		.VPB(VPWR),
-    `endif 
-        .GCLK(clk_g), 
-        .GATE(clk_gated_en), 
-        .CLK(PCLK)
-        );
-
-	wire		clk = clk_g;
+    `ifdef FPGA
+		wire clk = PCLK;
+	`else
+		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+		`ifdef USE_POWER_PINS 
+			.VPWR(VPWR), 
+			.VGND(VGND), 
+			.VNB(VGND),
+			.VPB(VPWR),
+		`endif
+			.GCLK(clk_g), 
+			.GATE(clk_gated_en), 
+			.CLK(PCLK)
+			);
+
+		wire		clk = clk_g;
+	`endif
 	wire		rst_n = PRESETn;
 
     wire                rst         = ~PRESETn;

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.v
@@ -90,19 +90,23 @@ module EF_I2C_APB # (
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
 
-    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-    `ifdef USE_POWER_PINS 
-        .VPWR(VPWR), 
-        .VGND(VGND), 
-        .VNB(VGND),
-		.VPB(VPWR),
-    `endif 
-        .GCLK(clk_g), 
-        .GATE(clk_gated_en), 
-        .CLK(PCLK)
-        );
-
-	wire		clk = clk_g;
+    `ifdef FPGA
+		wire clk = PCLK;
+	`else
+		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+		`ifdef USE_POWER_PINS 
+			.VPWR(VPWR), 
+			.VGND(VGND), 
+			.VNB(VGND),
+			.VPB(VPWR),
+		`endif
+			.GCLK(clk_g), 
+			.GATE(clk_gated_en), 
+			.CLK(PCLK)
+			);
+
+		wire		clk = clk_g;
+	`endif
 	wire		rst_n = PRESETn;
 
     wire                rst         = ~PRESETn;