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ARM64 - Optimize i % 2 #70599

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Jun 17, 2022
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f1e7232
Always morph GT_MOD for ARM64. Added lowering optimization for a full…
TIHan May 5, 2022
8205969
Remove space
TIHan May 5, 2022
98a4350
Match cases with mod 2 and long types
TIHan May 5, 2022
dd8556f
Minor tweak
TIHan May 5, 2022
b3c967e
Minor tweak
TIHan May 5, 2022
9b35e79
Minor tweak
TIHan May 5, 2022
2517c60
Do not add overflow/throwdivzero to the block if the second operand i…
TIHan May 5, 2022
c0b8b1a
Lets not modify whether or not we should have overflow/throwdivzero e…
TIHan May 5, 2022
e19661c
Merge branch 'main' into mod-opt-fix
TIHan May 12, 2022
d989b10
Perform the transformation in pre-order rationalization
TIHan May 16, 2022
44065c0
Merge branch 'mod-opt-fix' of github.com:TIHan/runtime into mod-opt-fix
TIHan May 16, 2022
7c43a37
Fix cns equality check
TIHan May 16, 2022
9c03bc6
Fixing build
TIHan May 16, 2022
6b3b7e5
Fixing build
TIHan May 16, 2022
574c17d
Fixing build
TIHan May 16, 2022
068bb7f
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan May 17, 2022
7628c7b
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan May 18, 2022
9d06be0
Merge branch 'mod-opt-fix' of github.com:TIHan/runtime into mod-opt-fix
TIHan May 18, 2022
e334dcf
Formatting
TIHan May 18, 2022
5400acc
Use correct cns
TIHan May 18, 2022
b10a443
Use correct cns
TIHan May 18, 2022
79d943a
Formatting
TIHan May 18, 2022
b3a6608
Moving to PostorderVisit
TIHan May 18, 2022
ca8c836
Moving to simple lowering and checking if node is closed
TIHan May 19, 2022
d2057b9
Merging
TIHan May 19, 2022
c3531f3
Fixing build
TIHan May 19, 2022
fe7e590
Added comment
TIHan May 20, 2022
6f6c1b1
Update flowgraph.cpp
TIHan May 20, 2022
611dc66
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan May 24, 2022
26784cc
Merge branch 'mod-opt-fix' of github.com:TIHan/runtime into mod-opt-fix
TIHan May 25, 2022
d78e4b5
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan Jun 1, 2022
51bd85b
Merging. Moving back to pre-order. Added regression test.
TIHan Jun 1, 2022
c2052ea
Do not need to check reverse ops as we just look for vars and constants
TIHan Jun 1, 2022
9501ae3
Remove extra var
TIHan Jun 2, 2022
cde3705
Renamed regression test. Added license header
TIHan Jun 6, 2022
4785bd9
Some tweaks
TIHan Jun 6, 2022
6ccee6f
Fixing build
TIHan Jun 6, 2022
fcf9517
Fixing build
TIHan Jun 7, 2022
68d8df9
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan Jun 7, 2022
e9d332f
Merge remote-tracking branch 'upstream/main' into mod-opt-fix
TIHan Jun 8, 2022
0452912
Added GT_CNEG_LT for ARM64 LIR to handle mod 2
TIHan Jun 9, 2022
80635b0
Added GT_CMP case for checking valid imm
TIHan Jun 9, 2022
edeb5b1
Formatting
TIHan Jun 9, 2022
a263cbc
Merging with main
TIHan Jun 12, 2022
f75e112
Fixing build
TIHan Jun 13, 2022
f06c8ca
Fixing build
TIHan Jun 13, 2022
d8e3937
Merging
TIHan Jun 16, 2022
6532108
Removed GTF_USE_FLAGS use
TIHan Jun 16, 2022
a76f6ee
Feedback
TIHan Jun 16, 2022
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31 changes: 21 additions & 10 deletions src/coreclr/jit/codegenarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10282,30 +10282,41 @@ void CodeGen::genCodeForAddEx(GenTreeOp* tree)
//
void CodeGen::genCodeForCond(GenTreeOp* tree)
{
assert(tree->OperIs(GT_CSNEG_MI));
assert(tree->OperIs(GT_CSNEG_MI, GT_CNEG_LT));
assert(!(tree->gtFlags & GTF_SET_FLAGS));
genConsumeOperands(tree);

instruction ins;
insCond cond;
switch (tree->OperGet())
{
case GT_CSNEG_MI:
{
ins = INS_csneg;
cond = INS_COND_MI;
instruction ins = INS_csneg;
insCond cond = INS_COND_MI;

regNumber dstReg = tree->GetRegNum();
regNumber op1Reg = tree->gtGetOp1()->GetRegNum();
regNumber op2Reg = tree->gtGetOp2()->GetRegNum();

GetEmitter()->emitIns_R_R_R_COND(ins, emitActualTypeSize(tree), dstReg, op1Reg, op2Reg, cond);
break;
}

case GT_CNEG_LT:
{
instruction ins = INS_cneg;
insCond cond = INS_COND_LT;

regNumber dstReg = tree->GetRegNum();
regNumber op1Reg = tree->gtGetOp1()->GetRegNum();

GetEmitter()->emitIns_R_R_COND(ins, emitActualTypeSize(tree), dstReg, op1Reg, cond);
break;
}

default:
unreached();
}

regNumber dstReg = tree->GetRegNum();
regNumber op1Reg = tree->gtGetOp1()->GetRegNum();
regNumber op2Reg = tree->gtGetOp2()->GetRegNum();

GetEmitter()->emitIns_R_R_R_COND(ins, emitActualTypeSize(tree), dstReg, op1Reg, op2Reg, cond);
genProduceReg(tree);
}

Expand Down
1 change: 1 addition & 0 deletions src/coreclr/jit/codegenarmarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -324,6 +324,7 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
break;

case GT_CSNEG_MI:
case GT_CNEG_LT:
genCodeForCond(treeNode->AsOp());
break;
#endif // TARGET_ARM64
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/gentree.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -9161,7 +9161,10 @@ GenTreeUseEdgeIterator::GenTreeUseEdgeIterator(GenTree* node)
m_state = -1;
return;

// Standard unary operators
// Standard unary operators
#ifdef TARGET_ARM64
case GT_CNEG_LT:
#endif // TARGET_ARM64
case GT_STORE_LCL_VAR:
case GT_STORE_LCL_FLD:
case GT_NOT:
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/jit/gtlist.h
Original file line number Diff line number Diff line change
Expand Up @@ -219,6 +219,7 @@ GTNODE(AND_NOT , GenTreeOp ,0,GTK_BINOP|DBK_NOTHIR)
GTNODE(ADDEX, GenTreeOp ,0,GTK_BINOP|DBK_NOTHIR) // Add with sign/zero extension.
GTNODE(BFIZ , GenTreeOp ,0,GTK_BINOP|DBK_NOTHIR) // Bitfield Insert in Zero.
GTNODE(CSNEG_MI , GenTreeOp ,0,GTK_BINOP|DBK_NOTHIR) // Conditional select, negate, minus result
GTNODE(CNEG_LT , GenTreeOp ,0,GTK_UNOP|DBK_NOTHIR) // Conditional, negate, signed less than result
#endif

//-----------------------------------------------------------------------------
Expand Down
84 changes: 54 additions & 30 deletions src/coreclr/jit/lowerarmarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,7 @@ bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const
case GT_LE:
case GT_GE:
case GT_GT:
case GT_CMP:
case GT_BOUNDS_CHECK:
return emitter::emitIns_valid_imm_for_cmp(immVal, size);
case GT_AND:
Expand Down Expand Up @@ -699,19 +700,7 @@ void Lowering::LowerRotate(GenTree* tree)
// Arguments:
// tree - the node to lower
//
// Return Value:
// A new tree node if it changed.
//
// Notes:
// {expr} % {cns}
// Logically turns into:
// let a = {expr}
// if a > 0 then (a & ({cns} - 1)) else -(-a & ({cns} - 1))
// which then turns into:
// and reg1, reg0, #({cns} - 1)
// negs reg0, reg0
// and reg0, reg0, #({cns} - 1)
// csneg reg0, reg1, reg0, mi
// TODO: We could do this optimization in morph but we do not have
// a conditional select op in HIR. At some point, we may
// introduce such an op.
Expand All @@ -722,12 +711,15 @@ void Lowering::LowerModPow2(GenTree* node)
GenTree* dividend = mod->gtGetOp1();
GenTree* divisor = mod->gtGetOp2();

JITDUMP("Lower: optimize X MOD POW2");

assert(divisor->IsIntegralConstPow2());

const var_types type = mod->TypeGet();
assert((type == TYP_INT) || (type == TYP_LONG));

ssize_t cnsValue = static_cast<ssize_t>(divisor->AsIntConCommon()->IntegralValue()) - 1;
ssize_t divisorCnsValue = static_cast<ssize_t>(divisor->AsIntConCommon()->IntegralValue());
ssize_t divisorCnsValueMinusOne = divisorCnsValue - 1;

BlockRange().Remove(divisor);

Expand All @@ -739,30 +731,62 @@ void Lowering::LowerModPow2(GenTree* node)
GenTree* dividend2 = comp->gtClone(dividend);
BlockRange().InsertAfter(dividend, dividend2);

GenTreeIntCon* cns = comp->gtNewIconNode(cnsValue, type);
GenTreeIntCon* cns = comp->gtNewIconNode(divisorCnsValueMinusOne, type);
BlockRange().InsertAfter(dividend2, cns);

GenTree* const trueExpr = comp->gtNewOperNode(GT_AND, type, dividend, cns);
BlockRange().InsertAfter(cns, trueExpr);
LowerNode(trueExpr);

GenTree* const neg = comp->gtNewOperNode(GT_NEG, type, dividend2);
neg->gtFlags |= GTF_SET_FLAGS;
BlockRange().InsertAfter(trueExpr, neg);

GenTreeIntCon* cns2 = comp->gtNewIconNode(cnsValue, type);
BlockRange().InsertAfter(neg, cns2);

GenTree* const falseExpr = comp->gtNewOperNode(GT_AND, type, neg, cns2);
BlockRange().InsertAfter(cns2, falseExpr);
LowerNode(falseExpr);

mod->ChangeOper(GT_CSNEG_MI);
mod->gtOp1 = trueExpr;
mod->gtOp2 = falseExpr;
if (divisorCnsValue == 2)
{
// {expr} % 2
// Logically turns into:
// let a = {expr}
// if a < 0 then -(a & 1) else (a & 1)
// which then turns into:
// and reg1, reg0, #1
// cmp reg0, #0
// cneg reg0, reg1, lt

GenTreeIntCon* cnsZero = comp->gtNewIconNode(0, type);
BlockRange().InsertAfter(trueExpr, cnsZero);

GenTree* const cmp = comp->gtNewOperNode(GT_CMP, type, dividend2, cnsZero);
cmp->gtFlags |= GTF_SET_FLAGS;
BlockRange().InsertAfter(cnsZero, cmp);
LowerNode(cmp);

JITDUMP("Lower: optimize X MOD POW2");
DISPNODE(mod);
mod->ChangeOper(GT_CNEG_LT);
mod->gtOp1 = trueExpr;
}
else
{
// {expr} % {cns}
// Logically turns into:
// let a = {expr}
// if a > 0 then (a & ({cns} - 1)) else -(-a & ({cns} - 1))
// which then turns into:
// and reg1, reg0, #({cns} - 1)
// negs reg0, reg0
// and reg0, reg0, #({cns} - 1)
// csneg reg0, reg1, reg0, mi

GenTree* const neg = comp->gtNewOperNode(GT_NEG, type, dividend2);
neg->gtFlags |= GTF_SET_FLAGS;
BlockRange().InsertAfter(trueExpr, neg);

GenTreeIntCon* cns2 = comp->gtNewIconNode(divisorCnsValueMinusOne, type);
BlockRange().InsertAfter(neg, cns2);

GenTree* const falseExpr = comp->gtNewOperNode(GT_AND, type, neg, cns2);
BlockRange().InsertAfter(cns2, falseExpr);
LowerNode(falseExpr);

mod->ChangeOper(GT_CSNEG_MI);
mod->gtOp1 = trueExpr;
mod->gtOp2 = falseExpr;
}

ContainCheckNode(mod);
}
Expand Down