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Fix ARM64 unsigned div by const perf regression #57400

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merged 2 commits into from
Aug 17, 2021
Merged

Fix ARM64 unsigned div by const perf regression #57400

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237ecdc
Fix ARM64 unsigned div by const perf regression
pentp Aug 14, 2021
3ec691f
Address feedback by @SingleAccretion
echesakov Aug 17, 2021
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10 changes: 9 additions & 1 deletion src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1853,8 +1853,16 @@ void CodeGen::genCodeForBinary(GenTreeOp* treeNode)

// The arithmetic node must be sitting in a register (since it's not contained)
assert(targetReg != REG_NA);
emitAttr attr = emitActualTypeSize(treeNode);

regNumber r = emit->emitInsTernary(ins, emitActualTypeSize(treeNode), treeNode, op1, op2);
// UMULL/SMULL is twice as fast for 32*32->64bit MUL
if ((oper == GT_MUL) && (targetType == TYP_LONG) && genActualTypeIsInt(op1) && genActualTypeIsInt(op2))
{
ins = treeNode->IsUnsigned() ? INS_umull : INS_smull;
attr = EA_4BYTE;
}

regNumber r = emit->emitInsTernary(ins, attr, treeNode, op1, op2);
assert(r == targetReg);

genProduceReg(treeNode);
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14 changes: 13 additions & 1 deletion src/coreclr/jit/lower.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5254,7 +5254,11 @@ bool Lowering::LowerUnsignedDivOrMod(GenTreeOp* divMod)
BlockRange().InsertBefore(divMod, preShiftBy, adjustedDividend);
firstNode = preShiftBy;
}
else if (type != TYP_I_IMPL)
else if (type != TYP_I_IMPL
#ifdef TARGET_ARM64
&& !simpleMul // On ARM64 we will use a 32x32->64 bit multiply as that's faster.
#endif
)
{
adjustedDividend = comp->gtNewCastNode(TYP_I_IMPL, adjustedDividend, true, TYP_U_IMPL);
BlockRange().InsertBefore(divMod, adjustedDividend);
Expand All @@ -5269,6 +5273,14 @@ bool Lowering::LowerUnsignedDivOrMod(GenTreeOp* divMod)
#endif

divisor->gtType = TYP_I_IMPL;

#ifdef TARGET_ARM64
if (simpleMul)
{
divisor->gtType = TYP_INT;
}
#endif

divisor->AsIntCon()->SetIconValue(magic);

if (isDiv && !postShift && type == TYP_I_IMPL)
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