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JIT: LowerHWIntrinsicCreate can create illegal IR #92766

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jakobbotsch opened this issue Sep 28, 2023 · 3 comments · Fixed by #93210
Closed

JIT: LowerHWIntrinsicCreate can create illegal IR #92766

jakobbotsch opened this issue Sep 28, 2023 · 3 comments · Fixed by #93210
Labels
area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
Milestone
9.0.0

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@jakobbotsch
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LowerHWIntrinsicCreate before:
N002 (  1,  1) [000017] -----------                   t17 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t17    byref  
N004 (  3,  4) [000054] -c---------                   t54 = ▌  LEA(b+4)  byref 
                                                            ┌──▌  t54    byref  
N005 (  4,  3) [000019] n---GO-----                   t19 = ▌  IND       float  <l:$203, c:$202>
                                                            ┌──▌  t3     float  
               [000089] ---XG------                   t89 = ▌  HWINTRINSIC simd16 float CreateScalarUnsafe
               [000090] -c---------                   t90 =    CNS_INT   int    1
N003 (  1,  2) [000004] -----------                    t4 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t89    simd16 
                                                            ├──▌  t90    int    
                                                            ├──▌  t4     float  
               [000091] ---XG------                   t91 = ▌  HWINTRINSIC simd16 float Insert
               [000092] -c---------                   t92 =    CNS_INT   int    2
N004 (  1,  2) [000005] -----------                    t5 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t91    simd16 
                                                            ├──▌  t92    int    
                                                            ├──▌  t5     float  
               [000093] ---XG------                   t93 = ▌  HWINTRINSIC simd16 float Insert
               [000094] -c---------                   t94 =    CNS_INT   int    3
N005 (  1,  2) [000006] -----------                    t6 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t93    simd16 
                                                            ├──▌  t94    int    
                                                            ├──▌  t6     float  
N006 (  7,  9) [000011] ---XG------                   t11 = ▌  HWINTRINSIC simd16 float Insert $2c0
                                                            ┌──▌  t11    simd16 
N007 ( 11, 12) [000014] DA-XG------                         ▌  STORE_LCL_VAR simd16 V07 tmp4         d:1 $1c1
               [000085] -----------                            IL_OFFSET void   INLRT @ 0x03D[--]
N001 (  1,  2) [000016] -----------                   t16 =    CNS_DBL   float  0.0000000000000000 $240
N006 (  1,  2) [000020] -----------                   t20 =    CNS_DBL   float  0.0000000000000000 $240
N007 (  1,  2) [000021] -----------                   t21 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t16    float  
                                                            ├──▌  t19    float  
                                                            ├──▌  t20    float  
                                                            ├──▌  t21    float  
N008 (  8, 10) [000026] ----GO-----                   t26 = ▌  HWINTRINSIC simd16 float Create $2c1
LowerHWIntrinsicCreate after:
               [000084] -----------                            IL_OFFSET void   INLRT @ 0x01C[--]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t1     byref  
N002 (  3,  2) [000003] ---XG------                    t3 = ▌  IND       float  <l:$201, c:$200>
N002 (  1,  1) [000017] -----------                   t17 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t17    byref  
N004 (  3,  4) [000054] -c---------                   t54 = ▌  LEA(b+4)  byref 
               [000096] -c---------                   t96 =    CNS_INT   int    1
                                                            ┌──▌  t54    byref  
N005 (  4,  3) [000019] n---GO-----                   t19 = ▌  IND       float  <l:$203, c:$202>
                                                            ┌──▌  t95    simd16 
                                                            ├──▌  t96    int    
                                                            ├──▌  t19    float  
               [000097] ----GO-----                   t97 = ▌  HWINTRINSIC simd16 float Insert
                                                            ┌──▌  t3     float  
               [000089] ---XG------                   t89 = ▌  HWINTRINSIC simd16 float CreateScalarUnsafe
               [000090] -c---------                   t90 =    CNS_INT   int    1
N003 (  1,  2) [000004] -----------                    t4 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t89    simd16 
                                                            ├──▌  t90    int    
                                                            ├──▌  t4     float  
               [000091] ---XG------                   t91 = ▌  HWINTRINSIC simd16 float Insert
               [000092] -c---------                   t92 =    CNS_INT   int    2
N004 (  1,  2) [000005] -----------                    t5 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t91    simd16 
                                                            ├──▌  t92    int    
                                                            ├──▌  t5     float  
               [000093] ---XG------                   t93 = ▌  HWINTRINSIC simd16 float Insert
               [000094] -c---------                   t94 =    CNS_INT   int    3
N005 (  1,  2) [000006] -----------                    t6 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t93    simd16 
                                                            ├──▌  t94    int    
                                                            ├──▌  t6     float  
N006 (  7,  9) [000011] ---XG------                   t11 = ▌  HWINTRINSIC simd16 float Insert $2c0
                                                            ┌──▌  t11    simd16 
N007 ( 11, 12) [000014] DA-XG------                         ▌  STORE_LCL_VAR simd16 V07 tmp4         d:1 $1c1
               [000085] -----------                            IL_OFFSET void   INLRT @ 0x03D[--]
               [000095] -----------                   t95 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
               [000098] -c---------                   t98 =    CNS_INT   int    2
N006 (  1,  2) [000020] -----------                   t20 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t97    simd16 
                                                            ├──▌  t98    int    
                                                            ├──▌  t20    float  
               [000099] ----GO-----                   t99 = ▌  HWINTRINSIC simd16 float Insert
               [000100] -----------                  t100 =    CNS_INT   int    3
N007 (  1,  2) [000021] -----------                   t21 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t99    simd16 
                                                            ├──▌  t100   int    
                                                            ├──▌  t21    float  
N008 (  8, 10) [000026] ----GO-----                   t26 = ▌  HWINTRINSIC simd16 float Insert $2c1
                                                            ┌──▌  t26    simd16

Notice that the use of t95 appears before the def.
@jakobbotsch jakobbotsch added this to the 9.0.0 milestone Sep 28, 2023
@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Sep 28, 2023
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ghost commented Sep 28, 2023

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details 
LowerHWIntrinsicCreate before:
N002 (  1,  1) [000017] -----------                   t17 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t17    byref  
N004 (  3,  4) [000054] -c---------                   t54 = ▌  LEA(b+4)  byref 
                                                            ┌──▌  t54    byref  
N005 (  4,  3) [000019] n---GO-----                   t19 = ▌  IND       float  <l:$203, c:$202>
                                                            ┌──▌  t3     float  
               [000089] ---XG------                   t89 = ▌  HWINTRINSIC simd16 float CreateScalarUnsafe
               [000090] -c---------                   t90 =    CNS_INT   int    1
N003 (  1,  2) [000004] -----------                    t4 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t89    simd16 
                                                            ├──▌  t90    int    
                                                            ├──▌  t4     float  
               [000091] ---XG------                   t91 = ▌  HWINTRINSIC simd16 float Insert
               [000092] -c---------                   t92 =    CNS_INT   int    2
N004 (  1,  2) [000005] -----------                    t5 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t91    simd16 
                                                            ├──▌  t92    int    
                                                            ├──▌  t5     float  
               [000093] ---XG------                   t93 = ▌  HWINTRINSIC simd16 float Insert
               [000094] -c---------                   t94 =    CNS_INT   int    3
N005 (  1,  2) [000006] -----------                    t6 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t93    simd16 
                                                            ├──▌  t94    int    
                                                            ├──▌  t6     float  
N006 (  7,  9) [000011] ---XG------                   t11 = ▌  HWINTRINSIC simd16 float Insert $2c0
                                                            ┌──▌  t11    simd16 
N007 ( 11, 12) [000014] DA-XG------                         ▌  STORE_LCL_VAR simd16 V07 tmp4         d:1 $1c1
               [000085] -----------                            IL_OFFSET void   INLRT @ 0x03D[--]
N001 (  1,  2) [000016] -----------                   t16 =    CNS_DBL   float  0.0000000000000000 $240
N006 (  1,  2) [000020] -----------                   t20 =    CNS_DBL   float  0.0000000000000000 $240
N007 (  1,  2) [000021] -----------                   t21 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t16    float  
                                                            ├──▌  t19    float  
                                                            ├──▌  t20    float  
                                                            ├──▌  t21    float  
N008 (  8, 10) [000026] ----GO-----                   t26 = ▌  HWINTRINSIC simd16 float Create $2c1
LowerHWIntrinsicCreate after:
               [000084] -----------                            IL_OFFSET void   INLRT @ 0x01C[--]
N001 (  1,  1) [000001] -----------                    t1 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t1     byref  
N002 (  3,  2) [000003] ---XG------                    t3 = ▌  IND       float  <l:$201, c:$200>
N002 (  1,  1) [000017] -----------                   t17 =    LCL_VAR   byref  V01 arg0         u:1 $81
                                                            ┌──▌  t17    byref  
N004 (  3,  4) [000054] -c---------                   t54 = ▌  LEA(b+4)  byref 
               [000096] -c---------                   t96 =    CNS_INT   int    1
                                                            ┌──▌  t54    byref  
N005 (  4,  3) [000019] n---GO-----                   t19 = ▌  IND       float  <l:$203, c:$202>
                                                            ┌──▌  t95    simd16 
                                                            ├──▌  t96    int    
                                                            ├──▌  t19    float  
               [000097] ----GO-----                   t97 = ▌  HWINTRINSIC simd16 float Insert
                                                            ┌──▌  t3     float  
               [000089] ---XG------                   t89 = ▌  HWINTRINSIC simd16 float CreateScalarUnsafe
               [000090] -c---------                   t90 =    CNS_INT   int    1
N003 (  1,  2) [000004] -----------                    t4 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t89    simd16 
                                                            ├──▌  t90    int    
                                                            ├──▌  t4     float  
               [000091] ---XG------                   t91 = ▌  HWINTRINSIC simd16 float Insert
               [000092] -c---------                   t92 =    CNS_INT   int    2
N004 (  1,  2) [000005] -----------                    t5 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t91    simd16 
                                                            ├──▌  t92    int    
                                                            ├──▌  t5     float  
               [000093] ---XG------                   t93 = ▌  HWINTRINSIC simd16 float Insert
               [000094] -c---------                   t94 =    CNS_INT   int    3
N005 (  1,  2) [000006] -----------                    t6 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t93    simd16 
                                                            ├──▌  t94    int    
                                                            ├──▌  t6     float  
N006 (  7,  9) [000011] ---XG------                   t11 = ▌  HWINTRINSIC simd16 float Insert $2c0
                                                            ┌──▌  t11    simd16 
N007 ( 11, 12) [000014] DA-XG------                         ▌  STORE_LCL_VAR simd16 V07 tmp4         d:1 $1c1
               [000085] -----------                            IL_OFFSET void   INLRT @ 0x03D[--]
               [000095] -----------                   t95 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
               [000098] -c---------                   t98 =    CNS_INT   int    2
N006 (  1,  2) [000020] -----------                   t20 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t97    simd16 
                                                            ├──▌  t98    int    
                                                            ├──▌  t20    float  
               [000099] ----GO-----                   t99 = ▌  HWINTRINSIC simd16 float Insert
               [000100] -----------                  t100 =    CNS_INT   int    3
N007 (  1,  2) [000021] -----------                   t21 =    CNS_DBL   float  0.0000000000000000 $240
                                                            ┌──▌  t99    simd16 
                                                            ├──▌  t100   int    
                                                            ├──▌  t21    float  
N008 (  8, 10) [000026] ----GO-----                   t26 = ▌  HWINTRINSIC simd16 float Insert $2c1
                                                            ┌──▌  t26    simd16

Notice that the use of t95 appears before the def.

Author: jakobbotsch
Assignees: -
Labels:

area-CodeGen-coreclr
Milestone: 9.0.0

@jakobbotsch
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jakobbotsch commented Sep 28, 2023 •
edited
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I hit this issue in #92768 for arm64. To hit it, change

if (ind->TypeIs(TYP_INT, TYP_LONG, TYP_DOUBLE, TYP_SIMD16))

to

if (ind->TypeIs(TYP_INT, TYP_LONG, TYP_FLOAT, TYP_DOUBLE, TYP_SIMD16))

and run SPMI replay (I hit it in libraries.pmi and realworld collections).

@jakobbotsch jakobbotsch mentioned this issue Oct 6, 2023
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The function assumes that the operands of the HW intrinsic come in order, which is just a basic assumption you cannot make for LIR.

jakobbotsch added a commit to jakobbotsch/runtime that referenced this issue Oct 9, 2023
@jakobbotsch
JIT: Fix LowerHWIntrinsicCreate LIR ordering issues
6e40556 
LowerHWIntrinsicCreate was assuming in many places that operand nodes
come in order, which is fundamentally not an assumption that can be made
for LIR.

Fix dotnet#92766
@jakobbotsch jakobbotsch mentioned this issue Oct 9, 2023
Merged
@ghost ghost added the in-pr There is an active PR which will close this issue when it is merged label Oct 9, 2023
This was referenced Oct 9, 2023
Open
Open
jakobbotsch added a commit that referenced this issue Oct 9, 2023
@jakobbotsch
JIT: Fix LowerHWIntrinsicCreate LIR ordering issues (#93210)
b4ae22c 
LowerHWIntrinsicCreate was assuming in many places that operand nodes
come in order, which is fundamentally not an assumption that can be made
for LIR.

Fix #92766
@ghost ghost removed the in-pr There is an active PR which will close this issue when it is merged label Oct 9, 2023
jakobbotsch added a commit to jakobbotsch/runtime that referenced this issue Oct 9, 2023
@jakobbotsch
JIT: Enable ldp reordering for TYP_FLOAT
37dd7c6 
This can be enabled now that dotnet#92766 is fixed.
@jakobbotsch jakobbotsch mentioned this issue Oct 9, 2023
Merged
jakobbotsch added a commit that referenced this issue Oct 10, 2023
@jakobbotsch
JIT: Enable ldp reordering for TYP_FLOAT (#93248)
5cb5daf 
This can be enabled now that #92766 is fixed.
@ghost ghost locked as resolved and limited conversation to collaborators Nov 8, 2023
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JIT: Fix LowerHWIntrinsicCreate LIR ordering issues jakobbotsch/runtime
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