130nm PLL Clock Multiplier IP

8x PLL Clock Multiplier IP on the Google-Skywater 130nm node.

Tested through spice simulations on skywater 130nm tt corner at room termperature

Generates 8x Multiplied Clock

Pre-Layout:

Frequency Obtained for 5Mhz input:    40MHz
Frequency Obtained for 12.5Mhz input:    100MHz

Duty Cycle obtained:    46% at 40MHz and 40.6% at 100MHz

Lock-in starts at ~80us for 100MHz and ~120us for 40Mhz

3rd-Order Loop Filter used [c1, c2, c3, r1, r2, r3]:    355fF, 350fF, 345fF, 490, 490, 490.

Post-Layout:

Frequency Obtained for 5Mhz input:    40MHz
Frequency Obtained for 12.5Mhz input:    100MHz

Duty Cycle obtained:    52.7% at 40MHz and 50% at 100MHz

Lock-in starts at ~22us for 100MHz and ~37us for 40Mhz

3rd-Order Loop Filter used [c1, c2, c3, r1, r2, r3]:    295fF, 300fF, 305fF, 490, 490, 490.

Contents:

1. Google-SkyWater 130nm PDK
2. Specifications
3. Pre-Layout Simulations
4. Layout
5. Post-Layout Simulations
6. EDA tools used
7. References
8. Instructions
9. Future Scope
10. Acknowledgements
11. Contact

Google-SkyWater 130nm PDK:

This PLL circuit is built on the Google-Skywater 130nm node. It is a mature 180nm-130nm hybrid technology originally developed internally by Cypress Semiconductor. The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources, which can be used to create manufacturable designs at SkyWater’s facility.

Specifications

Parameter	Description	min	typ	max	Unit	Conditions
VDD	Digital Supply	-	1.8	-	V	T = 27C
FCLKREF	Reference	5	-	12.5	MHz	T = 27C
FCLKOUT	Output Clock	40	-	100	MHz	PLL Mode, T = 27C
FCLKOUT	Output Clock	-	-	-	MHz	VCO Mode, T = 27C
JRMS	Jitter (rms)	-	-	-	ps	PLL_Mode
DC	Duty Cycle	52.7	-	50	%	T = 27C
TSET	Settling Time	~37	-	~22	us	T = 27C
CL	Load Capacitance	-	-	-	fF	T = 27C
IDD	Supply Current	-	-	-	fF	T = 27C

Pre-Layout Simulations

PLL Output (tt, 27degree Celcius):

Red: Reference Clock
Blue: Output Clock Divided by 8
Yellow: Down Signal
Brown: Up Signal
Pink (at top): ChargePump output

40Mhz Output:

-Close-up

-Steady State

Blue constantly overlapping Red indicating locked state

-Trend

100Mhz Output:

-Close-up

-Steady State

Blue constantly overlapping Red indicating lock

-Trend

Output Specs:
-Exact 40 Mhz

-Exact 100Mhz

Phase Frequency Detector 'Up' Signal :

Red: Clock 2
Blue: Clock 1
Orange: Up Signal
Green: Down Signal

Phase Frequency Detector 'Down' Signal :

Red: Clock 2
Blue: Clock 1
Orange: Up Signal
Green: Down Signal

Charge Pump response to 'Up' signal:

Red: Charge Pump Output Voltage

Charge Pump response to 'Down' signal:

Red: Charge Pump Output Voltage

Charge Pump output rise due to charge leakage:

Red: Charge Pump Output Voltage
Leakage: 40uV increase every 1us

Frequency Divider:

Red: Output Clock
Blue: Input Clock

*These above circuits were custom selected to improve stability and reduce area/power consumption.

Layout

Frequency Divider

Area: 29.92um square

Phase Frequency Detector

Area: 49.09um square

Mux

Area: 12.12um square

Charge Pump

Area: 132.29um square

Voltage Controlled Oscillator

Area: 57.73um square

Integrated PLL

Area: 496.03um square

Post-Layout Simulations

PLL Output (tt, 27degree Celcius):

Red: Reference Clock
Blue: Output Clock Divided by 8
Yellow: Down Signal
Brown: Up Signal
Pink (at top): ChargePump output

40Mhz Output:

-Close-up

-Steady State

Blue constantly overlapping Red indicating locked state

-Trend

100Mhz Output:

-Close-up

-Steady State

Blue constantly overlapping Red indicating locked state

-Trend

Output Specs:
-40 Mhz

-Exact 100Mhz

DRC:

Phase Frequency Detector 'Up' Signal :

Red: Clock 1
Blue: Clock 2
Orange: Up Signal
Green: Down Signal

Phase Frequency Detector 'Down' Signal :

Red: Clock1 2
Blue: Clock 2
Orange: Up Signal
Green: Down Signal

Charge Pump response to 'Up' signal:

Orange: Charge Pump Output Voltage
Red: Up Signal
Blue: Down Signal

Charge Pump response to 'Down' signal:

Orange: Charge Pump Output Voltage
Red: Up Signal
Blue: Down Signal

Charge Pump output rise due to charge leakage:

Orange: Charge Pump Output Voltage
Red: Up Signal
Blue: Down Signal
Leakage: < 0.05V in 100us

Frequency Divider:

Red: Input Clock
Blue: Output Clock

EDA Tools Used

• kicad (schematic capture)
  
• ngspice (simulation)
  
• magic (layout design)

References

[1] K.K. Abdul Majeed, Binsu J. Kailath, A Novel Phase Frequency Detector for a High Frequency PLL Design, Procedia Engineering, Volume 64, 2013, Pages 377-384, ISSN 1877-7058, doi: 10.1016/j.proeng.2013.09.110.

[2] X. Liu and A. N. Willson, "A pA-leakage CMOS charge pump for low-supply PLLs," 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 1037-1040, doi: 10.1109/MWSCAS.2010.5548821.

[3] Suman, Shruti & Sharma, Krishna. (2018). An Improved Performance Ring VCO: Analysis and Design. Ciência e Técnica Vitivinícola. 33. 254-0223.

[4] Karbalaei Mohammad Ali, M., Hashemipour, O. A simple and high performance charge pump based on the self-cascode transistor. Analog Integr Circ Sig Process 100, 633–638 (2019). doi: 10.1007/s10470-019-01478-y

[5] Y. -. Choi and D. -. Han, "Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1022-1025, Oct. 2006, doi: 10.1109/TCSII.2006.882122.

[6] Agrawal, Abhishek and Nikhil Saxena. “Comparative Analysis of High Speed FBB TSPC and E-TSPC Frequency Divider at 32 nm CMOS process,” International Journal of Trend in Research and Development (2017), Volume 4(1), ISSN: 2394-9333.

Instructions

For using magic for layout:

• Get magic v8.3.82 or above from here
  
• Place the tech file sky130.tech in the folder where you'll be using magic
  
• Open magic using the command: magic -T sky130

For using ngpice for simulations:

• Get ngspice from here or for ubuntu users, just use this command: sudo apt-get install ngspice
  
• Place the sky130nm.lib file and the Sky130_Primitives folder in the location where you'll be running ngspice
  
• Run the simulation: ngspice circuitname.cir

Future Scope

• Incorporation of Trimmer Codes.
• Incorporation of PVT compensation circuit.

Acknowledgements

• I thank Mr. Kunal Ghosh co-founder VSD, for providing me the opportunity to work on this wonderful project

Contact

• Lakshmi S (Author), MS ECE, Georgia Institute of Technology - [email protected]
• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - [email protected]