Merge with upstream (bytecodealliance#154)

RELEASES.md

@@ -758,7 +758,7 @@ Released 2023-09-20
   instead of at compile time.
   [#6807](https://github.com/bytecodealliance/wasmtime/pull/6807)
 
-* `Engine::detect_precompiled{,_file}` can be used to to determine whether some
+* `Engine::detect_precompiled{,_file}` can be used to determine whether some
   bytes or a file look like a precompiled module or a component.
   [#6832](https://github.com/bytecodealliance/wasmtime/pull/6832)
   [#6937](https://github.com/bytecodealliance/wasmtime/pull/6937)

cranelift/codegen/src/isa/aarch64/abi.rs

@@ -1190,10 +1190,11 @@ impl AArch64MachineDeps {
         for _ in 0..probe_count {
             insts.extend(Self::gen_sp_reg_adjust(-(guard_size as i32)));
 
-            insts.push(Self::gen_store_stack(
-                StackAMode::SPOffset(0, I8),
+            insts.push(Inst::gen_store(
+                AMode::SPOffset { off: 0, ty: I8 },
                 zero_reg(),
                 I32,
+                MemFlags::trusted(),
             ));
         }
 

cranelift/codegen/src/isa/riscv64/abi.rs

@@ -358,15 +358,17 @@ impl ABIMachineSpec for Riscv64MachineDeps {
             // sd   fp,0(sp)     ;; store old fp.
             // mv   fp,sp        ;; set fp to sp.
             insts.extend(Self::gen_sp_reg_adjust(-16));
-            insts.push(Self::gen_store_stack(
-                StackAMode::SPOffset(8, I64),
+            insts.push(Inst::gen_store(
+                AMode::SPOffset(8, I64),
                 link_reg(),
                 I64,
+                MemFlags::trusted(),
             ));
-            insts.push(Self::gen_store_stack(
-                StackAMode::SPOffset(0, I64),
+            insts.push(Inst::gen_store(
+                AMode::SPOffset(0, I64),
                 fp_reg(),
                 I64,
+                MemFlags::trusted(),
             ));
 
             if flags.unwind_info() {
@@ -395,15 +397,17 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         let mut insts = SmallVec::new();
 
         if frame_layout.setup_area_size > 0 {
-            insts.push(Self::gen_load_stack(
-                StackAMode::SPOffset(8, I64),
+            insts.push(Inst::gen_load(
                 writable_link_reg(),
+                AMode::SPOffset(8, I64),
                 I64,
+                MemFlags::trusted(),
             ));
-            insts.push(Self::gen_load_stack(
-                StackAMode::SPOffset(0, I64),
+            insts.push(Inst::gen_load(
                 writable_fp_reg(),
+                AMode::SPOffset(0, I64),
                 I64,
+                MemFlags::trusted(),
             ));
             insts.extend(Self::gen_sp_reg_adjust(16));
         }
@@ -483,10 +487,11 @@ impl ABIMachineSpec for Riscv64MachineDeps {
                         },
                     });
                 }
-                insts.push(Self::gen_store_stack(
-                    StackAMode::SPOffset(-(cur_offset as i64), ty),
+                insts.push(Inst::gen_store(
+                    AMode::SPOffset(-(cur_offset as i64), ty),
                     real_reg_to_reg(reg.to_reg()),
                     ty,
+                    MemFlags::trusted(),
                 ));
                 cur_offset += 8
             }
@@ -514,10 +519,11 @@ impl ABIMachineSpec for Riscv64MachineDeps {
                 RegClass::Float => F64,
                 RegClass::Vector => unimplemented!("Vector Clobber Restores"),
             };
-            insts.push(Self::gen_load_stack(
-                StackAMode::SPOffset(-cur_offset, ty),
+            insts.push(Inst::gen_load(
                 Writable::from_reg(real_reg_to_reg(reg.to_reg())),
+                AMode::SPOffset(-cur_offset, ty),
                 ty,
+                MemFlags::trusted(),
             ));
             cur_offset += 8
         }
@@ -1090,10 +1096,11 @@ impl Riscv64MachineDeps {
                 rs2: tmp.to_reg(),
             });
 
-            insts.push(Self::gen_store_stack(
-                StackAMode::SPOffset(0, I8),
+            insts.push(Inst::gen_store(
+                AMode::SPOffset(0, I8),
                 zero_reg(),
                 I32,
+                MemFlags::trusted(),
             ));
         }
 

cranelift/codegen/src/isa/x64/abi.rs

@@ -40,10 +40,10 @@ impl X64ABIMachineSpec {
 
             // TODO: It would be nice if we could store the imm 0, but we don't have insts for those
             // so store the stack pointer. Any register will do, since the stack is undefined at this point
-            insts.push(Self::gen_store_stack(
-                StackAMode::SPOffset(0, I8),
-                regs::rsp(),
+            insts.push(Inst::store(
                 I32,
+                regs::rsp(),
+                Amode::imm_reg(0, regs::rsp()),
             ));
         }
 

cranelift/codegen/src/isa/x64/lower.rs

@@ -4,7 +4,7 @@
 pub(super) mod isle;
 
 use crate::ir::pcc::{FactContext, PccResult};
-use crate::ir::{types, ExternalName, Inst as IRInst, LibCall, Opcode, Type};
+use crate::ir::{types, ExternalName, Inst as IRInst, InstructionData, LibCall, Opcode, Type};
 use crate::isa::x64::abi::*;
 use crate::isa::x64::inst::args::*;
 use crate::isa::x64::inst::*;
@@ -61,11 +61,10 @@ fn put_input_in_regs(ctx: &mut Lower<Inst>, spec: InsnInput) -> ValueRegs<Reg> {
 
     if let Some(c) = input.constant {
         // Generate constants fresh at each use to minimize long-range register pressure.
-        let from_bits = ty_bits(ty);
-        let (size, c) = if from_bits < 64 {
-            (OperandSize::Size32, c & ((1u64 << from_bits) - 1))
+        let size = if ty_bits(ty) < 64 {
+            OperandSize::Size32
         } else {
-            (OperandSize::Size64, c)
+            OperandSize::Size64
         };
         assert!(is_int_or_ref_ty(ty)); // Only used for addresses.
         let cst_copy = ctx.alloc_tmp(ty);
@@ -124,16 +123,18 @@ fn is_mergeable_load(
     // Just testing the opcode is enough, because the width will always match if
     // the type does (and the type should match if the CLIF is properly
     // constructed).
-    if insn_data.opcode() == Opcode::Load {
-        let offset = insn_data
-            .load_store_offset()
-            .expect("load should have offset");
+    if let &InstructionData::Load {
+        opcode: Opcode::Load,
+        offset,
+        ..
+    } = insn_data
+    {
         Some((
             InsnInput {
                 insn: src_insn,
                 input: 0,
             },
-            offset,
+            offset.into(),
         ))
     } else {
         None
@@ -261,35 +262,21 @@ fn lower_to_amode(ctx: &mut Lower<Inst>, spec: InsnInput, offset: i32) -> Amode
                 shift_amt,
             )
         } else {
-            for i in 0..=1 {
+            for input in 0..=1 {
                 // Try to pierce through uextend.
-                if let Some(uextend) = matches_input(
-                    ctx,
-                    InsnInput {
-                        insn: add,
-                        input: i,
-                    },
-                    Opcode::Uextend,
-                ) {
-                    if let Some(cst) = ctx.get_input_as_source_or_const(uextend, 0).constant {
-                        // Zero the upper bits.
-                        let input_size = ctx.input_ty(uextend, 0).bits() as u64;
-                        let shift: u64 = 64 - input_size;
-                        let uext_cst: u64 = (cst << shift) >> shift;
-
-                        let final_offset = (offset as i64).wrapping_add(uext_cst as i64);
-                        if let Ok(final_offset) = i32::try_from(final_offset) {
-                            let base = put_input_in_reg(ctx, add_inputs[1 - i]);
-                            return Amode::imm_reg(final_offset, base).with_flags(flags);
-                        }
-                    }
-                }
+                let (inst, inst_input) = if let Some(uextend) =
+                    matches_input(ctx, InsnInput { insn: add, input }, Opcode::Uextend)
+                {
+                    (uextend, 0)
+                } else {
+                    (add, input)
+                };
 
                 // If it's a constant, add it directly!
-                if let Some(cst) = ctx.get_input_as_source_or_const(add, i).constant {
+                if let Some(cst) = ctx.get_input_as_source_or_const(inst, inst_input).constant {
                     let final_offset = (offset as i64).wrapping_add(cst as i64);
                     if let Ok(final_offset) = i32::try_from(final_offset) {
-                        let base = put_input_in_reg(ctx, add_inputs[1 - i]);
+                        let base = put_input_in_reg(ctx, add_inputs[1 - input]);
                         return Amode::imm_reg(final_offset, base).with_flags(flags);
                     }
                 }

cranelift/codegen/src/machinst/buffer.rs

@@ -1635,8 +1635,11 @@ impl<I: VCodeInst> MachBuffer<I> {
 
     /// Set the `SourceLoc` for code from this offset until the offset at the
     /// next call to `end_srcloc()`.
-    pub fn start_srcloc(&mut self, loc: RelSourceLoc) {
-        self.cur_srcloc = Some((self.cur_offset(), loc));
+    /// Returns the current [CodeOffset] and [RelSourceLoc].
+    pub fn start_srcloc(&mut self, loc: RelSourceLoc) -> (CodeOffset, RelSourceLoc) {
+        let cur = (self.cur_offset(), loc);
+        self.cur_srcloc = Some(cur);
+        cur
     }
 
     /// Mark the end of the `SourceLoc` segment started at the last

cranelift/codegen/src/machinst/lower.rs

@@ -1218,7 +1218,16 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
     /// Get the value of a constant instruction (`iconst`, etc.) as a 64-bit
     /// value, if possible.
     pub fn get_constant(&self, ir_inst: Inst) -> Option<u64> {
-        self.inst_constants.get(&ir_inst).cloned()
+        self.inst_constants.get(&ir_inst).map(|&c| {
+            // The upper bits must be zero, enforced during legalization and by
+            // the CLIF verifier.
+            debug_assert_eq!(c, {
+                let input_size = self.output_ty(ir_inst, 0).bits() as u64;
+                let shift = 64 - input_size;
+                (c << shift) >> shift
+            });
+            c
+        })
     }
 
     /// Get the input as one of two options other than a direct register:

cranelift/filetests/src/runone.rs

@@ -176,7 +176,7 @@ impl FileUpdate {
         assert!(location.line_number > self.last_update.get());
         self.last_update.set(location.line_number);
 
-        // Read the old test file and calculate thte new line number we're
+        // Read the old test file and calculate the new line number we're
         // preserving up to based on how many lines prior to this have been
         // removed or added.
         let old_test = std::fs::read_to_string(&self.path)?;

crates/c-api/include/wasmtime.h

@@ -224,7 +224,7 @@ extern "C" {
 #endif
 
 /**
- * \brief Converts from the text format of WebAssembly to to the binary format.
+ * \brief Converts from the text format of WebAssembly to the binary format.
  *
  * \param wat this it the input pointer with the WebAssembly Text Format inside
  *        of it. This will be parsed and converted to the binary format.

crates/environ/src/component/translate/inline.rs

@@ -224,7 +224,7 @@ struct InlinerFrame<'a> {
 //
 // FIXME: this is cloned quite a lot and given the internal maps if this is a
 // perf issue we may want to `Rc` these fields. Note that this is only a perf
-// hit at compile-time though which we in general don't pay too too much
+// hit at compile-time though which we in general don't pay too much
 // attention to.
 #[derive(Default, Clone)]
 struct ComponentClosure<'a> {

crates/winch/src/builder.rs

@@ -3,21 +3,26 @@ use anyhow::{bail, Result};
 use std::sync::Arc;
 use target_lexicon::Triple;
 use wasmtime_cranelift::isa_builder::IsaBuilder;
-use wasmtime_environ::{CompilerBuilder, Setting};
+use wasmtime_environ::{CompilerBuilder, Setting, Tunables};
 use winch_codegen::{isa, TargetIsa};
 
 /// Compiler builder.
 struct Builder {
     inner: IsaBuilder<Result<Box<dyn TargetIsa>>>,
     cranelift: Box<dyn CompilerBuilder>,
+    tunables: Option<Tunables>,
 }
 
 pub fn builder(triple: Option<Triple>) -> Result<Box<dyn CompilerBuilder>> {
     let inner = IsaBuilder::new(triple.clone(), |triple| {
         isa::lookup(triple).map_err(|e| e.into())
     })?;
     let cranelift = wasmtime_cranelift::builder(triple)?;
-    Ok(Box::new(Builder { inner, cranelift }))
+    Ok(Box::new(Builder {
+        inner,
+        cranelift,
+        tunables: None,
+    }))
 }
 
 impl CompilerBuilder for Builder {
@@ -47,16 +52,22 @@ impl CompilerBuilder for Builder {
         self.inner.settings()
     }
 
-    fn set_tunables(&mut self, tunables: wasmtime_environ::Tunables) -> Result<()> {
+    fn set_tunables(&mut self, tunables: Tunables) -> Result<()> {
         assert!(tunables.winch_callable);
+        self.tunables = Some(tunables.clone());
         self.cranelift.set_tunables(tunables)?;
         Ok(())
     }
 
     fn build(&self) -> Result<Box<dyn wasmtime_environ::Compiler>> {
         let isa = self.inner.build()?;
         let cranelift = self.cranelift.build()?;
-        Ok(Box::new(Compiler::new(isa, cranelift)))
+        let tunables = self
+            .tunables
+            .as_ref()
+            .expect("set_tunables not called")
+            .clone();
+        Ok(Box::new(Compiler::new(isa, cranelift, tunables)))
     }
 
     fn enable_incremental_compilation(