fix: invertibility conditions DIVU and REMU #141
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# [0.4.0](v0.3.0...v0.4.0) (2021-06-14) ### Bug Fixes * **symbolic:** print actual progam exit status codes ([05d692e](05d692e)) * inverse value calculation for LHS of REMU ([#131](#131)) ([c24270a](c24270a)) * invertibility condition for SLTU (when `t != 0`) ([6947f52](6947f52)) * invertibility conditions DIVU and REMU ([#141](#141)) ([9c03995](9c03995)) * represent empty path condition as single true constant ([e1afdd6](e1afdd6)) * use ite to convert booleans to bitvectors ([5411f15](5411f15)) * **smt:** zero extend bitvectors for comp ops in external solver ([2576441](2576441)) * **test:** syntax errors in C* examples ([dc60453](dc60453)) ### Features * **symbolic:** add support for openat system call ([#20](#20)) ([de71a0c](de71a0c)) * create custom CLI command for SMT-lib file generation ([2e8eb46](2e8eb46)) * handle exit points with unknown satisfiability ([8891c64](8891c64)) ### Performance Improvements * switch rarity simulation to segmented memory ([7d31865](7d31865))
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🎉 This PR is included in version 0.4.0 🎉 The release is available on: Your semantic-release bot 📦🚀 |
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DIVU
Regarding the the special case that is invertible, but should not occur according to the assumption that target != current output. So far this case is handled as not invertible. This is just a suggestion to handle it as invertible.
REMU
This adds missing parenthesis and the case s == t => invertible
Summery of invertible, not invertible:
DIVU Lhs:
s = 0, t = ones => invertible, but should not happen as this means currently t = ones already
s = 0, t != ones => not invertible
t = ones, s != {0,1} => not invertible, overflow
DIVU Rhs:
t = s = 0 => invertible, but again should not happen
t = 0, s != ones => invertible
t = 0, s = ones => not invertible
t = ones, (s = ones) => invertible
t = ones, (s != ones) => invertible
s < t => not invertible