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Changes to the Cluster API used by the GPU Project #3714
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43b0fdf
Abstractify Cluster API to support custom cluster types
hansungk 056e62a
Add cluster-local bus (CLBUS)
hansungk 0dc13d7
fix seip connection when tile does not use supervisor
richardyrh 20ce83b
Don't connect NullIntSource to tileCeaseXbarNode of Cluster
hansungk 8c8b3f5
Merge branch 'dev' of https://github.com/chipsalliance/rocket-chip in…
richardyrh cf65449
Merge branch 'dev' of https://github.com/chipsalliance/rocket-chip in…
richardyrh c6fa6b9
[cluster] Add missing clock group connection for clbus
hansungk cd35968
Merge commit 'ea9979b1'
hansungk e84843f
Merge branch 'master' of https://github.com/chipsalliance/rocket-chip…
richardyrh 5b1ff5a
Merge branch 'upstream-master'
richardyrh 4687b06
move clbus to radiance
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Original file line number | Diff line number | Diff line change |
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@@ -19,10 +19,20 @@ import scala.collection.immutable.SortedMap | |
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case class ClustersLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachCluster]](Nil) | ||
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trait BaseClusterParams extends HierarchicalElementParams { | ||
val clusterId: Int | ||
} | ||
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abstract class InstantiableClusterParams[ClusterType <: Cluster] | ||
extends HierarchicalElementParams | ||
with BaseClusterParams { | ||
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): ClusterType | ||
} | ||
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case class ClusterParams( | ||
val clusterId: Int, | ||
val clockSinkParams: ClockSinkParameters = ClockSinkParameters() | ||
) extends HierarchicalElementParams { | ||
) extends InstantiableClusterParams[Cluster] { | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Are many of these changes intended to let you extend Cluster? |
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val baseName = "cluster" | ||
val uniqueName = s"${baseName}_$clusterId" | ||
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): Cluster = { | ||
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@@ -31,7 +41,7 @@ case class ClusterParams( | |
} | ||
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class Cluster( | ||
val thisClusterParams: ClusterParams, | ||
val thisClusterParams: BaseClusterParams, | ||
crossing: ClockCrossingType, | ||
lookup: LookupByClusterIdImpl)(implicit p: Parameters) extends BaseHierarchicalElement(crossing)(p) | ||
with Attachable | ||
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@@ -46,10 +56,12 @@ class Cluster( | |
lazy val allClockGroupsNode = ClockGroupIdentityNode() | ||
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val csbus = tlBusWrapperLocationMap(CSBUS(clusterId)) // like the sbus in the base subsystem | ||
val clbus = tlBusWrapperLocationMap(CLBUS(clusterId)) // like the sbus in the base subsystem | ||
val ccbus = tlBusWrapperLocationMap(CCBUS(clusterId)) // like the cbus in the base subsystem | ||
val cmbus = tlBusWrapperLocationMap.lift(CMBUS(clusterId)).getOrElse(csbus) | ||
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csbus.clockGroupNode := allClockGroupsNode | ||
clbus.clockGroupNode := allClockGroupsNode | ||
ccbus.clockGroupNode := allClockGroupsNode | ||
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val slaveNode = ccbus.inwardNode | ||
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@@ -66,7 +78,7 @@ class Cluster( | |
def toPlicDomain = this | ||
lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap) | ||
lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap) | ||
lazy val seipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap) | ||
lazy val seipNodes = totalTiles.filter(_._2.tileParams.core.useSupervisor).keys.map { i => (i, IntIdentityNode()) }.to(SortedMap) | ||
lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap) | ||
lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.to(SortedMap) | ||
lazy val nmiNodes = totalTiles.filter { case (i,t) => t.tileParams.core.useNMI } | ||
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@@ -79,7 +91,7 @@ class Cluster( | |
// TODO fix: shouldn't need to connect dummy notifications | ||
tileHaltXbarNode := NullIntSource() | ||
tileWFIXbarNode := NullIntSource() | ||
tileCeaseXbarNode := NullIntSource() | ||
// tileCeaseXbarNode := NullIntSource() | ||
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override lazy val module = new ClusterModuleImp(this) | ||
} | ||
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@@ -88,12 +100,12 @@ class ClusterModuleImp(outer: Cluster) extends BaseHierarchicalElementModuleImp[ | |
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case class InCluster(id: Int) extends HierarchicalLocation(s"Cluster$id") | ||
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class ClusterPRCIDomain( | ||
abstract class ClusterPRCIDomain[ClusterType <: Cluster]( | ||
clockSinkParams: ClockSinkParameters, | ||
crossingParams: HierarchicalElementCrossingParamsLike, | ||
clusterParams: ClusterParams, | ||
clusterParams: InstantiableClusterParams[ClusterType], | ||
lookup: LookupByClusterIdImpl) | ||
(implicit p: Parameters) extends HierarchicalElementPRCIDomain[Cluster](clockSinkParams, crossingParams) | ||
(implicit p: Parameters) extends HierarchicalElementPRCIDomain[ClusterType](clockSinkParams, crossingParams) | ||
{ | ||
val element = element_reset_domain { | ||
LazyModule(clusterParams.instantiate(crossingParams, lookup)) | ||
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@@ -104,19 +116,19 @@ class ClusterPRCIDomain( | |
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trait CanAttachCluster { | ||
type ClusterType <: Cluster | ||
type ClusterContextType <: DefaultHierarchicalElementContextType | ||
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def clusterParams: ClusterParams | ||
def clusterParams: InstantiableClusterParams[ClusterType] | ||
def crossingParams: HierarchicalElementCrossingParamsLike | ||
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def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = { | ||
def instantiate(allClusterParams: Seq[BaseClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain[_]])(implicit p: Parameters): ClusterPRCIDomain[ClusterType] = { | ||
val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName)) | ||
val cluster_prci_domain = LazyModule(new ClusterPRCIDomain( | ||
clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams))) | ||
val cluster_prci_domain = LazyModule(new ClusterPRCIDomain[ClusterType]( | ||
clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)) {}) | ||
cluster_prci_domain | ||
} | ||
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def connect(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connect(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
connectMasterPorts(domain, context) | ||
connectSlavePorts(domain, context) | ||
connectInterrupts(domain, context) | ||
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@@ -126,21 +138,21 @@ trait CanAttachCluster { | |
connectTrace(domain, context) | ||
} | ||
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def connectMasterPorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { | ||
def connectMasterPorts(domain: ClusterPRCIDomain[ClusterType], context: Attachable): Unit = { | ||
implicit val p = context.p | ||
val dataBus = context.locateTLBusWrapper(crossingParams.master.where) | ||
dataBus.coupleFrom(clusterParams.baseName) { bus => | ||
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) | ||
} | ||
} | ||
def connectSlavePorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { | ||
def connectSlavePorts(domain: ClusterPRCIDomain[ClusterType], context: Attachable): Unit = { | ||
implicit val p = context.p | ||
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) | ||
controlBus.coupleTo(clusterParams.baseName) { bus => | ||
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus | ||
} | ||
} | ||
def connectInterrupts(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connectInterrupts(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
implicit val p = context.p | ||
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domain.element.debugNodes.foreach { case (hartid, node) => | ||
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@@ -170,23 +182,23 @@ trait CanAttachCluster { | |
} | ||
} | ||
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def connectPRC(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connectPRC(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
implicit val p = context.p | ||
domain.element.allClockGroupsNode :*= context.allClockGroupsNode | ||
domain { | ||
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode | ||
} | ||
} | ||
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def connectOutputNotifications(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connectOutputNotifications(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
implicit val p = context.p | ||
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.tileHaltXbarNode) | ||
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.tileWFIXbarNode) | ||
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.tileCeaseXbarNode) | ||
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} | ||
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def connectInputConstants(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connectInputConstants(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
implicit val p = context.p | ||
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) | ||
domain.element.tileHartIdNodes.foreach { case (hartid, node) => | ||
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@@ -197,7 +209,7 @@ trait CanAttachCluster { | |
} | ||
} | ||
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def connectTrace(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { | ||
def connectTrace(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = { | ||
implicit val p = context.p | ||
domain.element.traceNodes.foreach { case (hartid, node) => | ||
val traceNexusNode = BundleBridgeBlockDuringReset[TraceBundle]( | ||
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@@ -212,23 +224,26 @@ trait CanAttachCluster { | |
} | ||
} | ||
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case class ClusterAttachParams( | ||
case class ClusterAttachParams ( | ||
clusterParams: ClusterParams, | ||
crossingParams: HierarchicalElementCrossingParamsLike | ||
) extends CanAttachCluster | ||
) extends CanAttachCluster { | ||
type ClusterType = Cluster | ||
} | ||
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case class CloneClusterAttachParams( | ||
sourceClusterId: Int, | ||
cloneParams: CanAttachCluster | ||
) extends CanAttachCluster { | ||
type ClusterType = cloneParams.ClusterType | ||
def clusterParams = cloneParams.clusterParams | ||
def crossingParams = cloneParams.crossingParams | ||
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override def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = { | ||
override def instantiate(allClusterParams: Seq[BaseClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain[_]])(implicit p: Parameters): ClusterPRCIDomain[ClusterType] = { | ||
require(instantiatedClusters.contains(sourceClusterId)) | ||
val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName)) | ||
val cluster_prci_domain = CloneLazyModule( | ||
new ClusterPRCIDomain(clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)), | ||
new ClusterPRCIDomain[ClusterType](clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)) {}, | ||
instantiatedClusters(sourceClusterId) | ||
) | ||
cluster_prci_domain | ||
|
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What is the difference between the CLBUS and the CSBUS?
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If you want the CLBUS to be totally private, you probably don't want it to the CCOH (ClusterCoherence) device, since that exposes cluster-external memory
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Ah, thanks for the heads up