Avoid import from chisel3.core

Close #1817
chipsalliance · Feb 7, 2019 · ddf9540 · ddf9540
1 parent e831ca3
commit ddf9540
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
@@ -10,7 +10,6 @@ import freechips.rocketchip.tile.LookupByHartId
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
-import chisel3.core.{DontCare, WireInit}
 import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.experimental._
 import TLMessages._