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Make BaseModule.name lazy #912

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Oct 28, 2018
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2 changes: 1 addition & 1 deletion chiselFrontend/src/main/scala/chisel3/core/Module.scala
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ abstract class BaseModule extends HasId {
def desiredName = this.getClass.getName.split('.').last

/** Legalized name of this module. */
final val name = Builder.globalNamespace.name(desiredName)
final lazy val name = Builder.globalNamespace.name(desiredName)

/** Returns a FIRRTL ModuleName that references this object
* @note Should not be called until circuit elaboration is complete
Expand Down
9 changes: 9 additions & 0 deletions src/test/scala/chiselTests/Module.scala
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,12 @@ class ModuleRewrap extends Module {
val inst2 = Module(inst)
}

class ModuleWrapper(gen: => Module) extends Module {
val io = IO(new Bundle{})
val child = Module(gen)
override lazy val desiredName = s"${child.desiredName}Wrapper"
}

class ModuleSpec extends ChiselPropSpec {

property("ModuleVec should elaborate") {
Expand Down Expand Up @@ -138,4 +144,7 @@ class ModuleSpec extends ChiselPropSpec {
"a" -> m.a, "b" -> m.b))
})
}
property("A desiredName parameterized by a submodule should work") {
Driver.elaborate(() => new ModuleWrapper(new ModuleWire)).name should be ("ModuleWireWrapper")
}
}