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Fix naming for RHS of named unapply expressions #3163
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Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named. Also, audit and improve the naming mdocs.
I've reviewed the impact on Verilog in some internal code and from my random sampling, lots of signals are now getting named and overall, the churn isn't too bad. There's a bit of churn because unnamed signals now have lower indices, eg. |
azidar
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Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named. Also, audit and improve the naming mdocs. (cherry picked from commit 262caa7) # Conflicts: # docs/src/cookbooks/naming.md
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* Fix naming for RHS of named unapply expressions (#3163) Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named. Also, audit and improve the naming mdocs. (cherry picked from commit 262caa7) # Conflicts: # docs/src/cookbooks/naming.md * Resolve backport conflicts --------- Co-authored-by: Jack Koenig <[email protected]>
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Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named. Also, audit and improve the naming mdocs.
azidar
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Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named. Also, audit and improve the naming mdocs.
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Previously, the naming plugin would not recurse for the RHS of an unapply, meaning that vals declared in blocks that ultimately return some result that is unapplied into some named Data would not be named.
The actual fix here is like 10 characters, but also see the tests and improvements to docs--the examples I reworked were because either they give bad results with MFC or are optimized in such a way that they don't show the purpose of the example (registers are useful for this)
Also, audit and improve the naming mdocs.
I've marked this for 3.6.x. I think we should get this into 3.6.0, the question is if we should do a 3.6.0-RC4 or if this is fine to sneak in to 3.6.0.
Contributor Checklist
docs/src
?Type of Improvement
API Impact
No impact
Backend Code Generation Impact
Fixes a bug in the intended behavior of the compiler plugin. I am evaluating the impact on SiFive Verilog. It might be substantial.
Desired Merge Strategy
Release Notes
This results in previously unnamed signals receiving names from the compiler plugin.
Reviewer Checklist (only modified by reviewer)
3.5.x
or3.6.x
depending on impact, API modification or big change:5.0.0
)?Enable auto-merge (squash)
, clean up the commit message, and label withPlease Merge
.Create a merge commit
.