API for probing internal signals

firrtl/src/main/scala/firrtl/ir/IR.scala

@@ -194,6 +194,13 @@ abstract class Literal extends Expression {
   val value: BigInt
   val width: Width
 }
+
+case class ProbeExpr(expr: Expression) extends Expression with UseSerializer {
+  def tpe = ProbeType(expr.tpe)
+}
+
+case class ProbeRead(expr: Expression, tpe: Type = UnknownType) extends Expression with UseSerializer
+
 case class UIntLiteral(value: BigInt, width: Width) extends Literal with UseSerializer {
   def tpe = UIntType(width)
 }
@@ -329,6 +336,17 @@ object Print {
   }
 }
 
+case class ProbeDefine(info: Info, sink: Expression, probeExpr: Expression) extends Statement with UseSerializer
+
+case class ProbeForceInitial(info: Info, probe: Expression, value: Expression) extends Statement with UseSerializer
+case class ProbeReleaseInitial(info: Info, probe: Expression) extends Statement with UseSerializer
+case class ProbeForce(info: Info, clock: Expression, cond: Expression, probe: Expression, value: Expression)
+    extends Statement
+    with UseSerializer
+case class ProbeRelease(info: Info, clock: Expression, cond: Expression, probe: Expression)
+    extends Statement
+    with UseSerializer
+
 // formal
 object Formal extends Enumeration {
   val Assert = Value("assert")
@@ -445,6 +463,9 @@ object GroundType {
   def unapply(ground: GroundType): Option[Width] = Some(ground.width)
 }
 abstract class AggregateType extends Type
+
+case class ProbeType(underlying: Type) extends Type with UseSerializer
+case class RWProbeType(underlying: Type) extends Type with UseSerializer
 case class UIntType(width: Width) extends GroundType with UseSerializer
 case class SIntType(width: Width) extends GroundType with UseSerializer
 

firrtl/src/main/scala/firrtl/ir/Serializer.scala

@@ -94,7 +94,9 @@ object Serializer {
     case ValidIf(cond, value, _) => b ++= "validif("; s(cond); b ++= ", "; s(value); b += ')'
     case SIntLiteral(value, width) =>
       b ++= "SInt"; s(width); b ++= "(\"h"; b ++= value.toString(16); b ++= "\")"
-    case other => b ++= other.serialize // Handle user-defined nodes
+    case ProbeExpr(expr)    => b ++= "probe("; s(expr); b += ')'
+    case ProbeRead(expr, _) => b ++= "read("; s(expr); b += ')'
+    case other              => b ++= other.serialize // Handle user-defined nodes
   }
 
   // Helper for some not-real Statements that only exist for Serialization
@@ -278,6 +280,16 @@ object Serializer {
     case firrtl.CDefMPort(info, name, _, mem, exps, direction) =>
       b ++= direction.serialize; b ++= " mport "; b ++= name; b ++= " = "; b ++= mem
       b += '['; s(exps.head); b ++= "], "; s(exps(1)); s(info)
+    case ProbeDefine(info, sink, probeExpr) =>
+      b ++= "define "; s(sink); b ++= " = "; s(probeExpr); s(info)
+    case ProbeForceInitial(info, probe, value) =>
+      b ++= "force_initial("; s(probe); b ++= ", "; s(value); b += ')'; s(info)
+    case ProbeReleaseInitial(info, probe) =>
+      b ++= "release_initial("; s(probe); b += ')'; s(info)
+    case ProbeForce(info, clock, cond, probe, value) =>
+      b ++= "force("; s(clock); b ++= ", "; s(cond); b ++= ", "; s(probe); b ++= ", "; s(value); b += ')'; s(info)
+    case ProbeRelease(info, clock, cond, probe) =>
+      b ++= "release("; s(clock); b ++= ", "; s(cond); b ++= ", "; s(probe); b += ')'; s(info)
     case other => b ++= other.serialize // Handle user-defined nodes
   }
 
@@ -309,6 +321,8 @@ object Serializer {
 
   private def s(node: Type)(implicit b: StringBuilder, indent: Int): Unit = node match {
     // Types
+    case ProbeType(underlying: Type) => b ++= "Probe<"; s(underlying); b += '>'
+    case RWProbeType(underlying: Type) => b ++= "RWProbe<"; s(underlying); b += '>'
     case UIntType(width: Width) => b ++= "UInt"; s(width)
     case SIntType(width: Width) => b ++= "SInt"; s(width)
     case BundleType(fields)    => b ++= "{ "; sField(fields, ", "); b += '}'

firrtl/src/test/scala/firrtlTests/SerializerSpec.scala

@@ -82,6 +82,50 @@ object SerializerSpec {
       "test"
     )
 
+  val probeModule: String =
+    """module probeModule :
+      |  input clock : Clock
+      |  input cond : UInt<1>
+      |  input in : UInt<8>
+      |  input inProbe : Probe<UInt<8>>
+      |  output out : UInt<8>
+
+      |  inst c of child
+      |  wire fooProbe : Probe<UInt<8>>
+      |  c.in <= in
+      |  define fooProbe = probe(c.in)
+      |  out <= read(out)
+      |  force_initial(inProbe, UInt<8>("h64"))
+      |  release_initial(inProbe)
+      |  force(clock, cond, inProbe, in)
+      |  release(clock, cond, inProbe)""".stripMargin
+
+  val probeModuleIR: Module =
+    Module(
+      NoInfo,
+      "probeModule",
+      Seq(
+        Port(NoInfo, "clock", Input, ClockType),
+        Port(NoInfo, "cond", Input, UIntType(IntWidth(1))),
+        Port(NoInfo, "in", Input, UIntType(IntWidth(8))),
+        Port(NoInfo, "inProbe", Input, ProbeType(UIntType(IntWidth(8)))),
+        Port(NoInfo, "out", Output, UIntType(IntWidth(8)))
+      ),
+      Block(
+        Seq(
+          DefInstance("c", "child"),
+          DefWire(NoInfo, "fooProbe", ProbeType(UIntType(IntWidth(8)))),
+          Connect(NoInfo, SubField(Reference("c"), "in"), Reference("in")),
+          ProbeDefine(NoInfo, Reference("fooProbe"), ProbeExpr(SubField(Reference("c"), "in"))),
+          Connect(NoInfo, Reference("out"), ProbeRead(Reference("out"))),
+          ProbeForceInitial(NoInfo, Reference("inProbe"), UIntLiteral(100, IntWidth(8))),
+          ProbeReleaseInitial(NoInfo, Reference("inProbe")),
+          ProbeForce(NoInfo, Reference("clock"), Reference("cond"), Reference("inProbe"), Reference("in")),
+          ProbeRelease(NoInfo, Reference("clock"), Reference("cond"), Reference("inProbe"))
+        )
+      )
+    )
+
 }
 
 /** used to test parsing and serialization of smems */
@@ -176,4 +220,25 @@ class SerializerSpec extends AnyFlatSpec with Matchers {
     SMemTestCircuit.circuit(ReadUnderWrite.New).serialize should include("new")
     SMemTestCircuit.circuit(ReadUnderWrite.Old).serialize should include("old")
   }
+
+  it should "support emitting Probe/RWProbe types and related expressions/statements" in {
+    val probeInt = DefWire(NoInfo, "foo", ProbeType(UIntType(IntWidth(3))))
+    Serializer.serialize(probeInt) should be("wire foo : Probe<UInt<3>>")
+
+    val rwProbeBundle = DefWire(
+      NoInfo,
+      "foo",
+      RWProbeType(
+        BundleType(
+          Seq(
+            Field("bar", Default, UIntType(IntWidth(32)))
+          )
+        )
+      )
+    )
+    Serializer.serialize(rwProbeBundle) should be("wire foo : RWProbe<{ bar : UInt<32>}>")
+
+    // check probe expressions and statements
+    Serializer.serialize(probeModuleIR) should be(probeModule)
+  }
 }