More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue)

src/main/scala/chisel3/util/circt/IsX.scala

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util.circt
+
+import chisel3._
+import chisel3.experimental.IntrinsicModule
+import chisel3.internal.Builder
+
+import circt.Intrinsic
+
+/** Create a module with a parameterized type which returns whether the input
+  * is a verilog 'x'.
+  */
+private class IsXIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.isX") {
+  val i = IO(Input(gen))
+  val found = IO(Output(UInt(1.W)))
+}
+
+object IsX {
+
+  /** Creates an intrinsic which returns whether the input is a verilog 'x'.
+    *
+    * @example {{{
+    * b := IsX(a)
+    * }}}
+    */
+  def apply[T <: Data](gen: T): Data = {
+    val inst = Module(new IsXIntrinsic(chiselTypeOf(gen)))
+    inst.i := gen
+    inst.found
+  }
+}

src/main/scala/chisel3/util/circt/PlusArgsTest.scala

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util.circt
+
+import chisel3._
+import chisel3.experimental.IntrinsicModule
+import chisel3.internal.Builder
+
+import circt.Intrinsic
+
+/** Create a module with a parameterized type which calls the verilog function
+  * \$test\$plusargs to test for the existence of the string str in the
+  * simulator command line.
+  */
+private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String)
+    extends IntrinsicModule("circt.plusargs.test", Map("FORMAT" -> str)) {
+  val found = IO(Output(UInt(1.W)))
+}
+
+object PlusArgsTest {
+
+  /** Creates an intrinsic which calls \$test\$plusargs.
+    *
+    * @example {{{
+    * b := PlusArgsTest(UInt<32.W>, "FOO")
+    * }}}
+    */
+  def apply[T <: Data](gen: T, str: String): Data = {
+    if (gen.isSynthesizable) {
+      val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str))
+      inst.found
+    } else {
+      val inst = Module(new PlusArgsTestIntrinsic(gen, str))
+      inst.found
+    }
+  }
+}

src/main/scala/chisel3/util/circt/PlusArgsValue.scala

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util.circt
+
+import chisel3._
+import chisel3.experimental.{FlatIO, IntrinsicModule}
+import chisel3.internal.Builder
+
+import circt.Intrinsic
+
+/** Create a module which generates a verilog \$plusargs\$value.  This returns a
+  * value as indicated by the format string and a flag for whether the value
+  * was found.
+  */
+private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String)
+    extends IntrinsicModule("circt.plusargs.value", Map("FORMAT" -> str)) {
+  val io = FlatIO(new Bundle {
+    val found = Output(UInt(1.W))
+    val result = Output(gen)
+  })
+}
+
+object PlusArgsValue {
+
+  /** Creates an intrinsic which calls \$test\$plusargs.
+    *
+    * @example {{{
+    * b := PlusArgsValue(UInt(32.W), "FOO=%d")
+    * b.found
+    * b.value
+    * }}}
+    */
+  def apply[T <: Data](gen: T, str: String) = {
+    if (gen.isSynthesizable) {
+      val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str))
+      inst.io
+    } else {
+      val inst = Module(new PlusArgsValueIntrinsic(gen, str))
+      inst.io
+    }
+  }
+}

src/main/scala/chisel3/util/circt/SizeOf.scala

@@ -2,37 +2,17 @@
 
 package chisel3.util.circt
 
-import scala.util.hashing.MurmurHash3
-
 import chisel3._
-import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule}
+import chisel3.experimental.IntrinsicModule
 import chisel3.internal.{Builder, BuilderContextCache}
 
-import circt.Intrinsic
-
-// We have to unique designedName per type, be we can't due to name conflicts
-// on bundles.  Thus we use a globally unique id.
-private object SizeOfGlobalIDGen {
-  private case object CacheKey extends BuilderContextCache.Key[Int]
-  def getID() = {
-    val oldID = Builder.contextCache.getOrElse(CacheKey, 0)
-    Builder.contextCache.put(CacheKey, oldID + 1)
-    oldID
-  }
-}
-
 /** Create a module with a parameterized type which returns the size of the type
   * as a compile-time constant.  This lets you write code which depends on the
   * results of type inference.
   */
-private class SizeOfIntrinsic[T <: Data](gen: T) extends ExtModule {
-  val i = IO(Input(gen));
+private class SizeOfIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.sizeof") {
+  val i = IO(Input(gen))
   val size = IO(Output(UInt(32.W)))
-  annotate(new ChiselAnnotation {
-    override def toFirrtl =
-      Intrinsic(toTarget, "circt.sizeof")
-  })
-  override val desiredName = "SizeOf_" + SizeOfGlobalIDGen.getID()
 }
 
 object SizeOf {
@@ -47,8 +27,8 @@ object SizeOf {
     * }}}
     */
   def apply[T <: Data](gen: T): Data = {
-    val sizeOfInst = Module(new SizeOfIntrinsic(chiselTypeOf(gen)))
-    sizeOfInst.i := gen
-    sizeOfInst.size
+    val inst = Module(new SizeOfIntrinsic(chiselTypeOf(gen)))
+    inst.i := gen
+    inst.size
   }
 }

src/test/scala/chiselTests/util/IsXSpec.scala

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.stage.ChiselGeneratorAnnotation
+import chisel3.testers.BasicTester
+import chisel3.util.circt.IsX
+import circt.stage.ChiselStage
+
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+import scala.io.Source
+
+private class IsXBundle extends Bundle {
+  val a = UInt()
+  val b = SInt()
+}
+
+private class IsXTop extends Module {
+  val io = IO(new Bundle {
+    val w = Input(UInt(65.W))
+    val x = Input(new IsXBundle)
+    val y = Input(UInt(65.W))
+    val outw = UInt(1.W)
+    val outx = UInt(1.W)
+    val outy = UInt(1.W)
+  })
+  io.outw := IsX(io.w)
+  io.outx := IsX(io.x)
+  io.outy := IsX(io.y)
+}
+
+class IsXSpec extends AnyFlatSpec with Matchers {
+  it should "Should work for types" in {
+    val fir = ChiselStage.emitCHIRRTL(new IsXTop)
+    println(fir)
+    (
+      (fir.split('\n').map(x => x.trim) should contain).allOf(
+        "intmodule IsXIntrinsic :",
+        "input i : UInt<65>",
+        "output found : UInt<1>",
+        "intrinsic = circt.isX",
+        "input i : { a : UInt, b : SInt}"
+      )
+    )
+  }
+}

src/test/scala/chiselTests/util/PlusArgsTestSpec.scala

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util.circt.PlusArgsTest
+import circt.stage.ChiselStage
+
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+import scala.io.Source
+
+private class PlusArgsTestTop extends Module {
+  val io = IO(new Bundle {
+    val w = Output(UInt(1.W))
+    val x = Output(UInt(1.W))
+    val z = Input(UInt(32.W))
+  })
+  io.w := PlusArgsTest(UInt(32.W), "FOO")
+  io.x := PlusArgsTest(io.z, "BAR")
+}
+
+class PlusArgsTestSpec extends AnyFlatSpec with Matchers {
+  it should "Should work for types" in {
+    val fir = ChiselStage.emitCHIRRTL(new PlusArgsTestTop)
+    println(fir)
+    (fir.split('\n').map(x => x.trim) should contain).allOf(
+      "intmodule PlusArgsTestIntrinsic :",
+      "output found : UInt<1>",
+      "intrinsic = circt.plusargs.test",
+      "parameter FORMAT = \"FOO\"",
+      "parameter FORMAT = \"BAR\""
+    )
+  }
+}

src/test/scala/chiselTests/util/PlusArgsValueSpec.scala

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util.circt.PlusArgsValue
+import circt.stage.ChiselStage
+
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+import scala.io.Source
+
+private class PlusArgsValueTop extends Module {
+  val io = IO(new Bundle {
+    val wf = Output(UInt(1.W))
+    val wv = Output(UInt(32.W))
+    val xf = Output(UInt(1.W))
+    val xv = Output(UInt(32.W))
+  })
+  val tmpw = PlusArgsValue(UInt(32.W), "FOO=%d")
+  val tmpx = PlusArgsValue(io.xv, "BAR=%d")
+  io.xf := tmpx.found
+  io.xv := tmpx.result
+}
+
+class PlusArgsValueSpec extends AnyFlatSpec with Matchers {
+  it should "Should work for types" in {
+    val fir = ChiselStage.emitCHIRRTL(new PlusArgsValueTop)
+    println(fir)
+    (fir.split('\n').map(x => x.trim) should contain).inOrder(
+      "intmodule PlusArgsValueIntrinsic :",
+      "output found : UInt<1>",
+      "output result : UInt<32>",
+      "intrinsic = circt.plusargs.value",
+      "parameter FORMAT = \"FOO=%d\"",
+      "parameter FORMAT = \"BAR=%d\""
+    )
+  }
+}

src/test/scala/chiselTests/util/SizeOfSpec.scala

@@ -1,64 +1,38 @@
+// SPDX-License-Identifier: Apache-2.0
+
 package chiselTests.util
 
 import chisel3._
-import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.testers.BasicTester
 import chisel3.util.circt.SizeOf
-
 import circt.stage.ChiselStage
 
-import firrtl.stage.FirrtlCircuitAnnotation
-
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
 import scala.io.Source
 
-class MyBundle extends Bundle {
+private class SizeOfBundle extends Bundle {
   val a = UInt()
   val b = SInt()
 }
 
-class SizeOfTop extends Module {
+private class SizeOfTop extends Module {
   val io = IO(new Bundle {
     val w = Input(UInt(65.W))
-    val x = Input(new MyBundle)
+    val x = Input(new SizeOfBundle)
     val outw = UInt(32.W)
     val outx = UInt(32.W)
   })
   io.outw := SizeOf(io.w)
   io.outx := SizeOf(io.x)
 }
 
-/** A test for intrinsics.  Since chisel is producing intrinsics as tagged
-  * extmodules (for now), we explicitly test the chirrtl and annotations rather
-  * than the processed firrtl or verilog.  It is worth noting that annotations
-  * are implemented (for now) in a way which makes the output valid for all
-  * firrtl compilers, hence we write a localized, not end-to-end test
-  */
 class SizeOfSpec extends AnyFlatSpec with Matchers {
   it should "Should work for types" in {
     val fir = ChiselStage.emitCHIRRTL(new SizeOfTop)
-    val a1 = """extmodule SizeOf_0""".r
-    (fir should include).regex(a1)
-    val b1 = """defname = SizeOf_0""".r
-    (fir should include).regex(b1)
-    val a2 = """extmodule SizeOf_1""".r
-    (fir should include).regex(a2)
-    val b2 = """defname = SizeOf_1""".r
-    (fir should include).regex(b2)
-
-    // The second elaboration uses a unique name since the Builder is reused (?)
-    val c = """Intrinsic\(~SizeOfTop\|SizeOf.*,circt.sizeof\)"""
-    ((new ChiselStage)
-      .execute(
-        args = Array("--target", "chirrtl"),
-        annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new SizeOfTop))
-      )
-      .flatMap {
-        case FirrtlCircuitAnnotation(circuit) => circuit.annotations
-        case _                                => None
-      }
-      .mkString("\n") should include).regex(c)
+    println(fir)
+    (fir.split('\n').map(x => x.trim) should contain)
+      .allOf("intmodule SizeOfIntrinsic :", "input i : UInt<65>", "output size : UInt<32>", "intrinsic = circt.sizeof")
   }
 }