Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

A name followed by the same name with an trailing underscore results in java.lang.NumberFormatException #3084

Open
sterin opened this issue Mar 12, 2023 · 3 comments

Comments

@sterin
Copy link

sterin commented Mar 12, 2023

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Construct hardware with some name, then construct additional hardware with the same name followed by an underscore. For example:

package foobar

import chisel3._

class Foo extends Module {
  val bar = RegInit(false.B)
  val bar_ = RegInit(false.B)
}

object EmitFoo {
  def main(args: Array[String]): Unit = {
    (new chisel3.stage.ChiselStage).emitVerilog(new Foo)
  }
}

What is the current behavior?

Fails, throws java.lang.NumberFormatException.

[info] running foobar.EmitFoo 
[error] (run-main-0) java.lang.NumberFormatException: For input string: ""
[error] java.lang.NumberFormatException: For input string: ""
[error]         at ... ()
[error]         at ... ()
[error]         at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
[error] stack trace is suppressed; run last Compile / bgRunMain for the full output
[error] Nonzero exit code: 1
[error] (Compile / runMain) Nonzero exit code: 1

What is the expected behavior?

Construct the appropriate hardware.

Please tell us about your environment:

Chisel version 3.5.6 and 3.6.0-RC2. Reproducible in the official Scastie environment of 3.6.0-RC2.

Does not reproduce in Chisel 3.5.5 and 3.5.4.

Official 3.6.0-RC2 Scastie:
https://scastie.scala-lang.org/jWaVv1vsSyGSG5I7Rvw9dw

3.5.6 Scastie:
https://scastie.scala-lang.org/fuqkiNCBTkCtnRWgJlLI2Q

Other Information

What is the use case for changing the behavior?

Chisel fails with a completely opaque error message.

@azidar
Copy link
Contributor

azidar commented Mar 13, 2023

@seldridge I believe this is an MFC issue?

@sterin
Copy link
Author

sterin commented Mar 13, 2023

@azidar It happens with Chisel 3.5.6 as well. I've added a 3.5.6 Scastie link to the issue. It is not clear from the stack trace, but it occurs inside the compiler plugin.

@azidar
Copy link
Contributor

azidar commented Mar 13, 2023

Ah yeah, sorry totally off base. Looks like a bug from #2856

liuyic00 added a commit to liuyic00/riscv-spec-core that referenced this issue Jun 14, 2024
liuyic00 added a commit to iscas-tis/riscv-spec-core that referenced this issue Jun 14, 2024
* fix: change uniqueId to avoid bug in systemVerilog

* fix: avoid naming bug caused by Chisel

see chipsalliance/chisel#3084
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants