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DataMirror.fullModulePorts and Opaque Types don't work as expected #2844

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mwachs5 opened this issue Nov 15, 2022 · 0 comments · Fixed by #2845
Closed

DataMirror.fullModulePorts and Opaque Types don't work as expected #2844

mwachs5 opened this issue Nov 15, 2022 · 0 comments · Fixed by #2845

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@mwachs5
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mwachs5 commented Nov 15, 2022

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Scastie: https://scastie.scala-lang.org/fdtxiIehRGu27O1LD16iZQ

import chisel3._
import chisel3.experimental.{DataMirror, OpaqueType}
import scala.collection.immutable.SeqMap

 class SingleElementRecord extends Record with OpaqueType with chisel3.experimental.AutoCloneType  {
    private val underlying = UInt(8.W)
    val elements = SeqMap("" -> underlying)

    def +(that: SingleElementRecord): SingleElementRecord = {
      val _w = Wire(new SingleElementRecord)
      _w.underlying := this.underlying + that.underlying
      _w
    }
  }

class InnerRecord extends Record with OpaqueType with chisel3.experimental.AutoCloneType {
    val k = new InnerInnerRecord
    val elements = SeqMap("" -> k)
  }

  class InnerInnerRecord extends Record with OpaqueType with chisel3.experimental.AutoCloneType {
    val k = new SingleElementRecord
    val elements = SeqMap("" -> k)
  }

  class NestedRecordModule extends Module {
    val in = IO(Input(new InnerRecord))
    val out = IO(Output(new InnerRecord))
    val inst = Module(new InnerModule)
    inst.io.foo := in
    out := inst.io.bar

    println(DataMirror.fullModulePorts(inst).mkString(",\n"))
  }

  class InnerModule extends Module {
    val io = IO(new Bundle {
      val foo = Input(new InnerRecord)
      val bar = Output(new InnerRecord)
    })

    io.bar := io.foo
  }

println(getVerilogString(new NestedRecordModule))

What is the current behavior?

(clock,InnerModule.clock: IO[Clock]),
(reset,InnerModule.reset: IO[Reset]),
(io,InnerModule.io: IO[AnonymousBundle]),
(io_bar,InnerModule.io.bar: IO[InnerRecord]),
(io_bar_,InnerModule.io.bar: IO[InnerInnerRecord]),
(io_bar__,InnerModule.io.bar: IO[SingleElementRecord]),
(io_bar___,InnerModule.io.bar: IO[UInt<8>]),
(io_foo,InnerModule.io.foo: IO[InnerRecord]),
(io_foo_,InnerModule.io.foo: IO[InnerInnerRecord]),
(io_foo__,InnerModule.io.foo: IO[SingleElementRecord]),
(io_foo___,InnerModule.io.foo: IO[UInt<8>])

What is the expected behavior?

I'm not sure, my best guess would be:

(clock,InnerModule.clock: IO[Clock]),
(reset,InnerModule.reset: IO[Reset]),
(io, InnerModule.io: IO[AnonymousBundle]),
(io_bar, InnerModule.io.bar: IO[InnerRecord]),
(io_bar, InnerModule.io.bar: IO[InnerInnerRecord]),
(io_bar, InnerModule.io.bar: IO[SingleElementRecord]),
(io_bar, InnerModule.io.bar: IO[UInt<8>]),
(io_foo, InnerModule.io.foo: IO[InnerRecord]),
(io_foo,InnerModule.io.foo: IO[InnerInnerRecord]),
(io_foo, InnerModule.io.foo: IO[SingleElementRecord]),
(io_foo, InnerModule.io.foo: IO[UInt<8>])

Please tell us about your environment:
- version: 3.5.5

Other Information

What is the use case for changing the behavior?

Getting accurate names for ports of opaque types

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