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Explicit readwrite ports for memories #238

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donggyukim opened this issue Jul 21, 2016 · 4 comments
Closed

Explicit readwrite ports for memories #238

donggyukim opened this issue Jul 21, 2016 · 4 comments
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@ducky64
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feature request
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3.4.x

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@donggyukim
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For now, there's no way to express readwrite ports in Chisel3. In Chisel2, they are inferred from read and write ports by checking their enable signals. I think there should be an explicit way as well as an implicit way to infer in firrtl.
@terpstra
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Strongly agree!

On Jul 21, 2016 1:27 PM, "Donggyu" [email protected] wrote:

For now, there's no way to express readwrite ports in Chisel3. In Chisel2,
they are inferred from read and write ports by checking their enable
signals. I think there should be an explicit way as well as an implicit way
to infer in firrtl.

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@ducky64 ducky64 changed the title No support for readwrite ports of memories Explicit readwrite ports for memories Feb 6, 2017
@ducky64
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ducky64 commented Feb 6, 2017

Resolution: there should be an explicit readwrite port for memories,

@ducky64 ducky64 added this to the 3.1.0 milestone Apr 18, 2017
@ducky64 ducky64 self-assigned this Apr 18, 2017
@ducky64 ducky64 modified the milestones: 3.1.0, 3.1.1 Dec 22, 2017
@edwardcwang edwardcwang modified the milestones: 3.1.1, 3.3.0 Jan 25, 2019
@jackkoenig
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Wait for chipsalliance/firrtl#1210

@azidar azidar modified the milestones: 3.3.0, 3.4.x Oct 27, 2020
mwachs5 pushed a commit that referenced this issue Dec 29, 2022
@jackkoenig
Update website to reflect 3.5.0 release (#238)
b4e77f7 
* Replace all uses of Y.5.0-RC with Y.5.0
* Change .gitmodules to track Y.5.x branches
* Update submodules `git submodule update --remote`
@jackkoenig
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This is done in #3190.

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@ducky64 @terpstra @azidar @donggyukim @jackkoenig @edwardcwang