Merge pull request #1426 from freechipsproject/1412-2

Fix Double Elaboration Backportably
chipsalliance · May 6, 2020 · e7b8e6e · e7b8e6e
2 parents 33cfe81 + 5e2ca44
commit e7b8e6e
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Showing 3 changed files with 21 additions and 9 deletions.
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -20,19 +20,19 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
 
   val targets: Seq[Dependency[Phase]] =
     Seq( Dependency[chisel3.stage.phases.Checks],
-         Dependency[chisel3.stage.phases.Elaborate],
          Dependency[chisel3.stage.phases.AddImplicitOutputFile],
          Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
          Dependency[chisel3.stage.phases.MaybeAspectPhase],
          Dependency[chisel3.stage.phases.Emitter],
          Dependency[chisel3.stage.phases.Convert],
          Dependency[chisel3.stage.phases.MaybeFirrtlStage] )
 
+  final lazy val phaseManager = new PhaseManager(targets) {
+    override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) )
+  }
+
   def run(annotations: AnnotationSeq): AnnotationSeq = try {
-    new PhaseManager(targets) { override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) ) }
-      .transformOrder
-      .map(firrtl.options.phases.DeletedWrapper(_))
-      .foldLeft(annotations)( (a, f) => f.transform(a) )
+    phaseManager.transform(annotations)
   } catch {
     case ce: ChiselException =>
       val stackTrace = if (!view[ChiselOptions](annotations).printFullStackTrace) {

diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala
@@ -30,10 +30,9 @@ class Emitter extends Phase {
          Dependency[AddImplicitOutputAnnotationFile],
          Dependency[MaybeAspectPhase] )
 
-  override def invalidates(phase: Phase): Boolean = phase match {
-    case _: Elaborate => true
-    case _ => false
-  }
+  override def optionalPrerequisiteOf = Seq(Dependency[Convert])
+
+  override def invalidates(phase: Phase): Boolean = false
 
   def transform(annotations: AnnotationSeq): AnnotationSeq = {
     val copts = view[ChiselOptions](annotations)

diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
@@ -8,6 +8,8 @@ import chisel3.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
+import firrtl.options.Dependency
+
 object ChiselStageSpec {
 
   class Foo extends MultiIOModule {
@@ -57,4 +59,15 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers {
     ChiselStage.convert(new Foo)
   }
 
+  behavior of "ChiselStage phase ordering"
+
+  it should "only run elaboration once" in new ChiselStageFixture {
+    info("Phase order is:\n" + stage.phaseManager.prettyPrint("    "))
+
+    val order = stage.phaseManager.flattenedTransformOrder.map(Dependency.fromTransform)
+
+    info("Elaborate only runs once")
+    exactly (1, order) should be (Dependency[chisel3.stage.phases.Elaborate])
+  }
+
 }