Convert ForceNamesSpec to use MFC (#2988)

Change the ForceNamesSpec, a test of the forceName Chisel API, to use
the MFC instead of the SFC.  This requires deleting all tests forcing
component names as this is not supported by the MFC.

Signed-off-by: Schuyler Eldridge <[email protected]>

src/test/scala/chiselTests/experimental/ForceNames.scala

@@ -5,8 +5,9 @@ package chiselTests
 import firrtl._
 import chisel3._
 import chisel3.experimental.annotate
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
-import chisel3.util.experimental.{forceName, ForceNameAnnotation, ForceNamesTransform, InlineInstance}
+import chisel3.stage.ChiselGeneratorAnnotation
+import chisel3.util.experimental.{forceName, InlineInstance}
+import circt.stage.ChiselStage
 import firrtl.annotations.{Annotation, ReferenceTarget}
 import firrtl.options.{Dependency, TargetDirAnnotation}
 import firrtl.stage.RunFirrtlTransformAnnotation
@@ -20,7 +21,6 @@ object ForceNamesHierarchy {
     val inst = Module(new Wrapper)
     inst.in := in
     out := inst.out
-    forceName(out, "outt")
   }
   class Wrapper extends Module with InlineInstance {
     val in = IO(Input(UInt(3.W)))
@@ -35,28 +35,6 @@ object ForceNamesHierarchy {
     val out = IO(Output(UInt(3.W)))
     out := in
   }
-  class RenamePortsExample extends Module {
-    val in = IO(Input(UInt(3.W)))
-    val out = IO(Output(UInt(3.W)))
-    val inst = Module(new MyLeaf)
-    inst.in := in
-    out := inst.out
-    forceName(inst.in, "inn")
-  }
-  class ConflictingName extends Module {
-    val in = IO(Input(UInt(3.W)))
-    val out = IO(Output(UInt(3.W)))
-    out := in
-    forceName(out, "in")
-  }
-  class BundleName extends Module {
-    val in = IO(new Bundle {
-      val a = Input(UInt(3.W))
-      val b = Input(UInt(3.W))
-    })
-    val out = IO(Output(UInt(3.W)))
-    out := in.a + in.b
-  }
 }
 
 class ForceNamesSpec extends ChiselFlatSpec {
@@ -67,21 +45,14 @@ class ForceNamesSpec extends ChiselFlatSpec {
     inputAnnos: Seq[Annotation] = Nil,
     info:       LogLevel.Value = LogLevel.None
   ): Iterable[String] = {
-    def stage = new ChiselStage {
-      override val targets = Seq(
-        Dependency[chisel3.stage.phases.Elaborate],
-        Dependency[chisel3.stage.phases.Convert],
-        Dependency[firrtl.stage.phases.Compiler]
-      )
-    }
+    val stage = new ChiselStage
 
     val annos = List(
       TargetDirAnnotation("test_run_dir/ForceNames"),
-      LogLevelAnnotation(info),
       ChiselGeneratorAnnotation(() => dut)
     ) ++ inputAnnos
 
-    val ret = stage.execute(Array(), annos)
+    val ret = stage.execute(Array("--target", "systemverilog"), annos)
     val verilog = ret.collectFirst {
       case e: EmittedVerilogCircuitAnnotation => e.value.value
     }.get
@@ -92,36 +63,4 @@ class ForceNamesSpec extends ChiselFlatSpec {
     val verilog = run(new ForceNamesHierarchy.WrapperExample, "wrapper")
     exactly(1, verilog) should include("MyLeaf inst")
   }
-  "Force Names on an instance port" should "work" in {
-    val verilog = run(new ForceNamesHierarchy.RenamePortsExample, "instports")
-    atLeast(1, verilog) should include("input  [2:0] inn")
-  }
-  "Force Names with a conflicting name" should "error" in {
-    intercept[CustomTransformException] {
-      run(new ForceNamesHierarchy.ConflictingName, "conflicts")
-    }
-  }
-  "Force Names of an intermediate bundle" should "error" in {
-    intercept[CustomTransformException] {
-      run(
-        new ForceNamesHierarchy.BundleName,
-        "bundlename",
-        Seq(ForceNameAnnotation(ReferenceTarget("BundleName", "BundleName", Nil, "in", Nil), "inn"))
-      )
-    }
-  }
-  "Force Name of non-hardware value" should "error" in {
-    class Example extends Module {
-      val tpe = UInt(8.W)
-      forceName(tpe, "foobar")
-
-      val in = IO(Input(tpe))
-      val out = IO(Output(tpe))
-      out := in
-    }
-
-    a[ChiselException] shouldBe thrownBy {
-      circt.stage.ChiselStage.elaborate(new Example)
-    }
-  }
 }