Merge branch 'master' into unary-not-fix

chipsalliance · Jan 17, 2019 · abdc1c3 · abdc1c3
2 parents 75caf7e + 685790b
commit abdc1c3
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Showing 5 changed files with 47 additions and 43 deletions.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -225,30 +225,14 @@ abstract class BaseModule extends HasId {
       }
     }
 
-    /** Recursively suggests names to supported "container" classes
-      * Arbitrary nestings of supported classes are allowed so long as the
-      * innermost element is of type HasId
-      * (Note: Map is Iterable[Tuple2[_,_]] and thus excluded)
-      */
-    def nameRecursively(prefix: String, nameMe: Any): Unit =
-      nameMe match {
-        case (id: HasId) => name(id, prefix)
-        case Some(elt) => nameRecursively(prefix, elt)
-        case (iter: Iterable[_]) if iter.hasDefiniteSize =>
-          for ((elt, i) <- iter.zipWithIndex) {
-            nameRecursively(s"${prefix}_${i}", elt)
-          }
-        case _ => // Do nothing
-      }
-
     /** Scala generates names like chisel3$util$Queue$$ram for private vals
       * This extracts the part after $$ for names like this and leaves names
       * without $$ unchanged
       */
     def cleanName(name: String): String = name.split("""\$\$""").lastOption.getOrElse(name)
 
     for (m <- getPublicFields(rootClass)) {
-      nameRecursively(cleanName(m.getName), m.invoke(this))
+      Builder.nameRecursively(cleanName(m.getName), m.invoke(this), name)
     }
 
     names

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -294,6 +294,21 @@ private[chisel3] object Builder {
     lastStack
   }
 
+  /** Recursively suggests names to supported "container" classes
+    * Arbitrary nestings of supported classes are allowed so long as the
+    * innermost element is of type HasId
+    * (Note: Map is Iterable[Tuple2[_,_]] and thus excluded)
+    */
+  def nameRecursively(prefix: String, nameMe: Any, namer: (HasId, String) => Unit): Unit = nameMe match {
+    case (id: HasId) => namer(id, prefix)
+    case Some(elt) => nameRecursively(prefix, elt, namer)
+    case (iter: Iterable[_]) if iter.hasDefiniteSize =>
+      for ((elt, i) <- iter.zipWithIndex) {
+        nameRecursively(s"${prefix}_${i}", elt, namer)
+      }
+    case _ => // Do nothing
+  }
+
   def errors: ErrorLog = dynamicContext.errors
   def error(m: => String): Unit = if (dynamicContextVar.value.isDefined) errors.error(m)
   def warning(m: => String): Unit = if (dynamicContextVar.value.isDefined) errors.warning(m)

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Namer.scala b/chiselFrontend/src/main/scala/chisel3/internal/Namer.scala
@@ -84,10 +84,7 @@ class NamingContext {
     closed = true
     for ((ref, suffix) <- items) {
       // First name the top-level object
-      ref match {
-        case nameable: chisel3.internal.HasId => nameable.suggestName(prefix + suffix)
-        case _ =>
-      }
+      chisel3.internal.Builder.nameRecursively(prefix + suffix, ref, (id, name) => id.suggestName(name))
 
       // Then recurse into descendant contexts
       if (descendants.containsKey(ref)) {

diff --git a/src/test/resources/chisel3/VerilogVendingMachine.v b/src/test/resources/chisel3/VerilogVendingMachine.v
@@ -10,35 +10,38 @@ module VerilogVendingMachine(
 );
   parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4;
   reg [2:0] state;
-  wire [2:0] next_state;
 
   assign dispense = (state == sOk) ? 1'd1 : 1'd0;
 
-  always @(*) begin
-    case (state)
-      sIdle: if (nickel) next_state <= s5;
-             else if (dime) next_state <= s10;
-             else next_state <= state;
-      s5: if (nickel) next_state <= s10;
-             else if (dime) next_state <= s15;
-             else next_state <= state;
-      s10: if (nickel) next_state <= s15;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      s15: if (nickel) next_state <= sOk;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      sOk: next_state <= sIdle;
-    endcase
-  end
-
-  // Go to next state
   always @(posedge clock) begin
     if (reset) begin
       state <= sIdle;
     end else begin
-      state <= next_state;
+      case (state)
+      sIdle: begin
+        if (nickel) state <= s5;
+        else if (dime) state <= s10;
+        else state <= state;
+      end
+      s5: begin
+        if (nickel) state <= s10;
+        else if (dime) state <= s15;
+        else state <= state;
+      end
+      s10: begin
+        if (nickel) state <= s15;
+        else if (dime) state <= sOk;
+        else state <= state;
+      end
+      s15: begin
+        if (nickel) state <= sOk;
+        else if (dime) state <= sOk;
+        else state <= state;
+      end
+      sOk: begin
+        state <= sIdle;
+      end
+      endcase
     end
   end
 endmodule
-
diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -67,6 +67,11 @@ class NamedModule extends NamedModuleTester {
     val myA = expectName(1.U + myNested, "test_myA")
     val myB = expectName(myA +& 2.U, "test_myB")
     val myC = expectName(myB +& 3.U, "test_myC")
+
+    val myD = Seq(myC +& 1.U, myC +& 2.U)
+    for ((d, i) <- myD.zipWithIndex)
+      expectName(d, s"test_myD_$i")
+
     myC +& 4.U  // named at enclosing scope
   }