Don't emit implicit clock warnings when an explicit clock is used (#3313

)
chipsalliance · Jun 1, 2023 · 9e39201 · 9e39201
1 parent f2ae014
commit 9e39201
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
@@ -484,7 +484,7 @@ sealed class SyncReadMem[T <: Data] private[chisel3] (
   )(
     implicit sourceInfo: SourceInfo
   ): T =
-    _readWrite_impl(idx, data, en, isWrite, clock, true)
+    _readWrite_impl(idx, data, en, isWrite, clock, false)
 
   /** @group SourceInfoTransformMacro */
   private def _readWrite_impl(
@@ -605,7 +605,7 @@ sealed class SyncReadMem[T <: Data] private[chisel3] (
   )(
     implicit evidence: T <:< Vec[_],
     sourceInfo:        SourceInfo
-  ) = masked_readWrite_impl(idx, writeData, mask, en, isWrite, clock, true)
+  ) = masked_readWrite_impl(idx, writeData, mask, en, isWrite, clock, false)
 
   private def masked_readWrite_impl(
     addr:    UInt,