Add asBool, deprecate toBool

chiselFrontend/src/main/scala/chisel3/core/Assert.scala

@@ -53,7 +53,7 @@ object assert { // scalastyle:ignore object.name
 
   def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) {
     val escLine = line.replaceAll("%", "%%")
-    when (!(cond || Module.reset.toBool)) {
+    when (!(cond || Module.reset.asBool)) {
       val fmt = message match {
         case Some(msg) =>
           s"Assertion failed: $msg\n    at $escLine\n"
@@ -80,7 +80,7 @@ object assert { // scalastyle:ignore object.name
 object stop { // scalastyle:ignore object.name
   /** Terminate execution with a failure code. */
   def apply(code: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
-    when (!Module.reset.toBool) {
+    when (!Module.reset.asBool) {
       pushCommand(Stop(sourceInfo, Builder.forcedClock.ref, code))
     }
   }

chiselFrontend/src/main/scala/chisel3/core/Bits.scala

@@ -78,6 +78,15 @@ abstract class Element extends Data {
   */
 private[chisel3] sealed trait ToBoolable extends Element {
 
+  /** Casts this $coll to a [[Bool]]
+    *
+    * @note The width must be known and equal to 1
+    */
+  final def asBool(): Bool = macro SourceInfoWhiteboxTransform.noArg
+
+  /** @group SourceInfoTransformMacro */
+  def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
+
   /** Casts this $coll to a [[Bool]]
     *
     * @note The width must be known and equal to 1
@@ -420,13 +429,17 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
     do_asUInt
   }
 
-  final def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+  final def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     width match {
       case KnownWidth(1) => this(0)
-      case _ => throwException(s"can't covert UInt<$width> to Bool")
+      case _ => throwException(s"can't covert ${this.getClass.getSimpleName}$width to Bool")
     }
   }
 
+  @chiselRuntimeDeprecated
+  @deprecated("Use asBool instead", "3.2")
+  final def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = do_asBool
+
   /** Concatenation operator
     *
     * @param that a hardware component

chiselFrontend/src/main/scala/chisel3/core/Printf.scala

@@ -86,7 +86,7 @@ object printf { // scalastyle:ignore object.name
     * @param pable [[Printable]] to print
     */
   def apply(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
-    when (!Module.reset.toBool) {
+    when (!Module.reset.asBool) {
       printfWithoutReset(pable)
     }
   }

src/main/scala/chisel3/compatibility.scala

@@ -250,7 +250,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val Mux = chisel3.core.Mux
   type Reset = chisel3.core.Reset
 
-  implicit def resetToBool(reset: Reset): Bool = reset.toBool
+  implicit def resetToBool(reset: Reset): Bool = reset.asBool
 
   import chisel3.core.Param
   abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.core.BlackBox(params) {

src/main/scala/chisel3/testers/BasicTester.scala

@@ -25,7 +25,7 @@ class BasicTester extends Module() {
     */
   def stop()(implicit sourceInfo: SourceInfo) {
     // TODO: rewrite this using library-style SourceInfo passing.
-    when (!reset.toBool) {
+    when (!reset.asBool) {
       pushCommand(Stop(sourceInfo, clock.ref, 0))
     }
   }

src/main/scala/chisel3/util/Bitwise.scala

@@ -69,7 +69,7 @@ object Fill {
       case 0 => UInt(0.W)
       case 1 => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
-        Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
+        Mux(x.asBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ =>
         val nBits = log2Ceil(n + 1)
         val p2 = Array.ofDim[UInt](nBits)

src/main/scala/chisel3/util/ImplicitConversions.scala

@@ -13,5 +13,5 @@ object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
   implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
-  implicit def booleanToBool(x: Boolean): Bool = x.asBool
+  implicit def booleanToBool(x: Boolean): Bool = x.B
 }

src/test/scala/chiselTests/AsTypeOfTester.scala

@@ -51,7 +51,7 @@ class AsTypeOfTruncationTester extends BasicTester {
 }
 
 class ResetAsTypeOfBoolTester extends BasicTester {
-  assert(reset.asTypeOf(Bool()) === reset.toBool)
+  assert(reset.asTypeOf(Bool()) === reset.asBool)
   stop()
 }
 

src/test/scala/chiselTests/Assert.scala

@@ -10,7 +10,7 @@ import chisel3.util._
 class FailingAssertTester() extends BasicTester {
   assert(false.B)
   // Wait to come out of reset
-  val (_, done) = Counter(!reset.toBool, 4)
+  val (_, done) = Counter(!reset.asBool, 4)
   when (done) {
     stop()
   }
@@ -19,7 +19,7 @@ class FailingAssertTester() extends BasicTester {
 class SucceedingAssertTester() extends BasicTester {
   assert(true.B)
   // Wait to come out of reset
-  val (_, done) = Counter(!reset.toBool, 4)
+  val (_, done) = Counter(!reset.asBool, 4)
   when (done) {
     stop()
   }
@@ -38,7 +38,7 @@ class PipelinedResetTester extends BasicTester {
 
   module.reset := RegNext(RegNext(RegNext(reset)))
 
-  val (_, done) = Counter(!reset.toBool, 4)
+  val (_, done) = Counter(!reset.asBool, 4)
   when (done) {
     stop()
   }

src/test/scala/chiselTests/MultiClockSpec.scala

@@ -55,7 +55,7 @@ class MultiClockSubModuleTest extends BasicTester {
 /** Test withReset changing the reset of a Reg */
 class WithResetTest extends BasicTester {
   val reset2 = WireInit(false.B)
-  val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) }
+  val reg = withReset(reset2 || reset.asBool) { RegInit(0.U(8.W)) }
   reg := reg + 1.U
 
   val (cycle, done) = Counter(true.B, 10)

src/test/scala/chiselTests/UIntOps.scala

@@ -80,15 +80,15 @@ class GoodBoolConversion extends Module {
     val u = Input(UInt(1.W))
     val b = Output(Bool())
   })
-  io.b := io.u.toBool
+  io.b := io.u.asBool
 }
 
 class BadBoolConversion extends Module {
   val io = IO(new Bundle {
     val u = Input(UInt(5.W))
     val b = Output(Bool())
   })
-  io.b := io.u.toBool
+  io.b := io.u.asBool
 }
 
 class NegativeShift(t: => Bits) extends Module {