Fix some old style warnings for good measure

core/src/main/scala/chisel3/Aggregate.scala

@@ -230,7 +230,8 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
     * @note the length of this Vec must match the length of the input Seq
     */
   def := (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = {
-    require(this.length == that.length, s"Cannot assign to a Vec of length ${this.length} from a Seq of different length ${that.length}")
+    require(this.length == that.length,
+      s"Cannot assign to a Vec of length ${this.length} from a Seq of different length ${that.length}")
     for ((a, b) <- this zip that)
       a := b
   }
@@ -578,7 +579,8 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
           }
         case field: EnumType => {
           if (!(field typeEquivalent value)) {
-            throw new BundleLiteralException(s"field $fieldName $field specified with non-type-equivalent enum value $value")
+            throw new BundleLiteralException(
+              s"field $fieldName $field specified with non-type-equivalent enum value $value")
           }
           val litArg = valueBinding match {
             case ElementLitBinding(litArg) => litArg

core/src/main/scala/chisel3/Data.scala

@@ -44,7 +44,8 @@ object SpecifiedDirection {
       case (SpecifiedDirection.Flip, thisDirection) => SpecifiedDirection.flip(thisDirection)
     }
 
-  private[chisel3] def specifiedDirection[T<:Data](source: T)(dir: SpecifiedDirection)(implicit compileOptions: CompileOptions): T = {
+  private[chisel3] def specifiedDirection[T<:Data](source: T)(
+    dir: SpecifiedDirection)(implicit compileOptions: CompileOptions): T = {
     if (compileOptions.checkSynthesizable) {
       requireIsChiselType(source)
     }

core/src/main/scala/chisel3/Mem.scala

@@ -29,7 +29,8 @@ object Mem {
   def apply[T <: Data](size: Int, t: T): Mem[T] = macro MemTransform.apply[T]
 
   /** @group SourceInfoTransformMacro */
-  def do_apply[T <: Data](size: BigInt, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Mem[T] = {
+  def do_apply[T <: Data](size: BigInt, t: T)(
+    implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Mem[T] = {
     if (compileOptions.declaredTypeMustBeUnbound) {
       requireIsChiselType(t, "memory type")
     }

core/src/main/scala/chisel3/Num.scala

@@ -305,4 +305,4 @@ trait NumObject {
         throw new ChiselException(s"Error converting BigDecimal $value to BigInt, binary point must be known, not $x")
     }
   }
-}
+}

core/src/main/scala/chisel3/Printf.scala

@@ -27,7 +27,8 @@ object printf { // scalastyle:ignore object.name
       } else if (x == '\t') {
         "\\t"
       } else {
-        require(x.toInt >= 32, s"char ${x} to Int ${x.toInt} must be >= 32") // TODO \xNN once FIRRTL issue #59 is resolved
+        // TODO \xNN once FIRRTL issue #59 is resolved
+        require(x.toInt >= 32, s"char ${x} to Int ${x.toInt} must be >= 32")
         x
       }
     }

core/src/main/scala/chisel3/dontTouch.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package chisel3
 
 import chisel3.experimental.{ChiselAnnotation, annotate, requireIsHardware}

core/src/main/scala/chisel3/experimental/Analog.scala

@@ -5,7 +5,8 @@ package chisel3.experimental
 import chisel3.internal.firrtl.Width
 import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.internal._
-import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt}
+import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString,
+  Printable, RawModule, SpecifiedDirection, UInt}
 
 import scala.collection.mutable
 

core/src/main/scala/chisel3/internal/BiConnect.scala

@@ -318,7 +318,9 @@ private[chisel3] object BiConnect {
 
     // Not quite sure where left and right are compared to current module
     // so just error out
-    else throw UnknownRelationException
+    else {
+      throw UnknownRelationException
+    }
   }
 
   // This function checks if analog element-level attaching is allowed, then marks the Analog as connected

core/src/main/scala/chisel3/internal/Builder.scala

@@ -447,7 +447,7 @@ object DynamicNamingStack {
     }
     prefixRef
   }
-  
+
   def length() : Int = Builder.namingStackOption.get.length
 }
 

core/src/main/scala/chisel3/internal/MonoConnect.scala

@@ -259,6 +259,8 @@ private[chisel3] object MonoConnect {
 
     // Not quite sure where left and right are compared to current module
     // so just error out
-    else throw UnknownRelationException
+    else {
+      throw UnknownRelationException
+    }
   }
 }

core/src/main/scala/chisel3/internal/Namer.scala

@@ -149,6 +149,6 @@ class NamingStack {
       namingStack.top.addDescendant(prefixRef, until)
     }
   }
-  
+
   def length() : Int = namingStack.length
 }

macros/src/main/scala/chisel3/internal/naming/NamingAnnotations.scala

@@ -112,7 +112,7 @@ class NamingTransforms(val c: Context) {
     }
   }
 
-  /** Applies the val name transform to a class body. 
+  /** Applies the val name transform to a class body.
     * Closes context on top level or return local context to englobing context.
     * Closing context only makes sense when top level a Module.
     * A Module is always the naming top level.
@@ -128,7 +128,7 @@ class NamingTransforms(val c: Context) {
     if($globalNamingStack.length == 1){
       $contextVar.namePrefix("")
     }
-    $globalNamingStack.popReturnContext(this, $contextVar) 
+    $globalNamingStack.popReturnContext(this, $contextVar)
     """
   }
 

src/main/scala/chisel3/aop/Select.scala

@@ -13,7 +13,7 @@ import scala.collection.mutable
 /** Use to select Chisel components in a module, after that module has been constructed
   * Useful for adding additional Chisel annotations or for use within an [[Aspect]]
   */
-object Select {
+object Select {  // scalastyle:off number.of.methods
 
   /** Return just leaf components of expanded node
     *
@@ -223,7 +223,9 @@ object Select {
     check(module)
     val sensitivitySignals = getIntermediateAndLeafs(signal).toSet
     val predicatedConnects = mutable.ArrayBuffer[PredicatedConnect]()
-    val isPort = module._component.get.asInstanceOf[DefModule].ports.flatMap{ p => getIntermediateAndLeafs(p.id) }.contains(signal)
+    val isPort = module._component.get.asInstanceOf[DefModule].ports.flatMap {
+      p => getIntermediateAndLeafs(p.id)
+    }.contains(signal)
     var prePredicates: Seq[Predicate] = Nil
     var seenDef = isPort
     searchWhens(module, (cmd: Command, preds) => {
@@ -235,14 +237,16 @@ object Select {
           val effected = getEffected(loc).toSet
           if(sensitivitySignals.intersect(effected).nonEmpty) {
             val expData = getData(exp)
-            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
+            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(
+              x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
             predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = false)
           }
         case BulkConnect(_, loc@Node(d: Data), exp) =>
           val effected = getEffected(loc).toSet
           if(sensitivitySignals.intersect(effected).nonEmpty) {
             val expData = getData(exp)
-            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
+            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(
+              x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
             predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = true)
           }
         case other =>
@@ -276,7 +280,9 @@ object Select {
     val printfs = mutable.ArrayBuffer[Printf]()
     searchWhens(module, (cmd: Command, preds: Seq[Predicate]) => {
       cmd match {
-        case chisel3.internal.firrtl.Printf(_, clock, pable) => printfs += Printf(preds, pable, getId(clock).asInstanceOf[Clock])
+        case chisel3.internal.firrtl.Printf(_, clock, pable) => {
+          printfs += Printf(preds, pable, getId(clock).asInstanceOf[Clock])
+        }
         case other =>
       }
     })

src/main/scala/chisel3/aop/injecting/InjectStatement.scala

@@ -15,7 +15,10 @@ import firrtl.annotations.{Annotation, ModuleTarget, NoTargetAnnotation, SingleT
   * @param modules Additional modules that may be instantiated by s
   * @param annotations Additional annotations that should be passed down compiler
   */
-case class InjectStatement(module: ModuleTarget, s: firrtl.ir.Statement, modules: Seq[firrtl.ir.DefModule], annotations: Seq[Annotation]) extends SingleTargetAnnotation[ModuleTarget] {
+case class InjectStatement(module: ModuleTarget, s: firrtl.ir.Statement,
+                           modules: Seq[firrtl.ir.DefModule],
+                           annotations: Seq[Annotation]
+                          ) extends SingleTargetAnnotation[ModuleTarget] {
   val target: ModuleTarget = module
   override def duplicate(n: ModuleTarget): Annotation = this.copy(module = n)
 }

src/main/scala/chisel3/stage/phases/AspectPhase.scala

@@ -28,9 +28,11 @@ class AspectPhase extends Phase {
         Nil
       case other => Seq(other)
     }
-    if(dut.isDefined) {
+    if (dut.isDefined) {
       val newAnnotations = aspects.flatMap { _.resolveAspect(dut.get) }
       remainingAnnotations ++ newAnnotations
-    } else annotations
+    } else {
+      annotations
+    }
   }
 }

src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala

@@ -13,8 +13,10 @@ class MaybeAspectPhase extends Phase with PreservesAll[Phase] {
   override val prerequisites = Seq(Dependency[Elaborate])
 
   def transform(annotations: AnnotationSeq): AnnotationSeq = {
-    if(annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) {
+    if (annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) {
       new AspectPhase().transform(annotations)
-    } else annotations
+    } else {
+      annotations
+    }
   }
 }

src/main/scala/chisel3/util/Decoupled.scala

@@ -311,7 +311,7 @@ object Queue
       enq: ReadyValidIO[T],
       entries: Int = 2,
       pipe: Boolean = false,
-      flow: Boolean = false): IrrevocableIO[T] = {    
+      flow: Boolean = false): IrrevocableIO[T] = {
     val deq = apply(enq, entries, pipe, flow)
     require(entries > 0, "Zero-entry queues don't guarantee Irrevocability")
     val irr = Wire(new IrrevocableIO(chiselTypeOf(deq.bits)))

src/main/scala/chisel3/util/Lookup.scala

@@ -13,9 +13,9 @@ import chisel3._
   *
   * @param addr common select for cases, shared (same) across all list elements
   * @param default default value for each list element, should the address not match any case
-  * @param mapping list of cases, where each entry consists of a [[chisel3.util.BitPat BitPath]] (compared against addr) and
-  *                a list of elements (same length as default) that is the output value for that
-  *                element (will have the same index in the output).
+  * @param mapping list of cases, where each entry consists of a [[chisel3.util.BitPat BitPath]]
+  *                (compared against addr) and a list of elements (same length as default) that
+  *                is the output value for that element (will have the same index in the output).
   *
   * @example {{{
   * ListLookup(2.U,  // address for comparison
@@ -44,8 +44,8 @@ object ListLookup {
   *
   * @param addr address to select between cases
   * @param default default value should the address not match any case
-  * @param mapping list of cases, where each entry consists of a [[chisel3.util.BitPat BitPat]] (compared against addr) and the
-  *          output value if the BitPat matches
+  * @param mapping list of cases, where each entry consists of a [[chisel3.util.BitPat BitPat]]
+  *                (compared against addr) and the output value if the BitPat matches
   */
 object Lookup {
   def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T =

src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala

@@ -154,8 +154,8 @@ class LoadMemoryTransform extends Transform {
 
     val modulesByName = circuit.modules.collect { case module: firrtl.ir.Module =>  module.name -> module }.toMap
 
-    /* Walk the module and for memories that are annotated with [[LoadMemoryAnnotation]]s generate the bindable modules for
-     * Verilog emission.
+    /* Walk the module and for memories that are annotated with [[LoadMemoryAnnotation]]s
+     * generate the bindable modules for Verilog emission.
      * @param myModule module being searched for memories
      */
     def processModule(myModule: DefModule): DefModule = {