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add svsim to mill
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sequencer committed Apr 10, 2023
1 parent 2c56bf8 commit 04580b9
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Showing 2 changed files with 35 additions and 1 deletion.
12 changes: 12 additions & 0 deletions build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,16 @@ class Firrtl(val crossScalaVersion: String)
def scoptIvy = v.scopt
}

object svsim extends mill.Cross[Svsim](v.scalaCrossVersions: _*)

class Svsim(val crossScalaVersion: String)
extends common.SvsimModule
with ChiselPublishModule
with CrossSbtModule
with ScalafmtModule {
def millSourcePath = super.millSourcePath / os.up / "svsim"
}

object firrtlut extends mill.Cross[FirrtlUnitTest](v.scalaCrossVersions: _*)

class FirrtlUnitTest(val crossScalaVersion: String)
Expand Down Expand Up @@ -163,6 +173,8 @@ class Chisel(val crossScalaVersion: String)
with ScalafmtModule {
override def millSourcePath = super.millSourcePath / os.up

def svsimModule = svsim(crossScalaVersion)

def macrosModule = macros(crossScalaVersion)

def coreModule = core(crossScalaVersion)
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24 changes: 23 additions & 1 deletion common.sc
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,26 @@ trait FirrtlModule
)
}

trait SvsimModule
extends ScalaModule {
}

trait SvsimUnitTestModule
extends ScalaModule {
def svsimModule: SvsimModule

def scalatestIvy: Dep

def scalacheckIvy: Dep

override def moduleDeps = Seq(svsimModule)

override def ivyDeps = super.ivyDeps() ++ Agg(
scalatestIvy,
scalacheckIvy
)
}

trait FirrtlUnitTestModule
extends TestModule
with ScalaModule
Expand Down Expand Up @@ -143,11 +163,13 @@ trait ChiselModule
with HasMacroAnnotations {
def macrosModule: MacrosModule

def svsimModule: SvsimModule

def coreModule: CoreModule

override def scalacPluginClasspath = T(super.scalacPluginClasspath() ++ Agg(pluginModule.jar()))

override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, coreModule)
override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, coreModule, svsimModule)
}

trait ChiselUnitTestModule
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