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Winch: Fix handled operand sizes in vpshuf #10041

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merged 1 commit into from
Jan 17, 2025
Merged

Winch: Fix handled operand sizes in vpshuf #10041

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4 changes: 2 additions & 2 deletions winch/codegen/src/isa/x64/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -566,7 +566,7 @@ impl Assembler {
assert!(dst.to_reg().is_float());

let op = match size {
OperandSize::S64 => AvxOpcode::Vpshufd,
OperandSize::S32 => AvxOpcode::Vpshufd,
_ => unimplemented!(),
};

Expand All @@ -591,7 +591,7 @@ impl Assembler {

let op = match size {
OperandSize::S16 => AvxOpcode::Vpshuflw,
OperandSize::S64 => AvxOpcode::Vpshufd,
OperandSize::S32 => AvxOpcode::Vpshufd,
_ => unimplemented!(),
};

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8 changes: 4 additions & 4 deletions winch/codegen/src/isa/x64/masm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -352,7 +352,7 @@ impl Masm for MacroAssembler {
dst.to_reg(),
dst,
Self::vpshuf_mask_for_64_bit_splats(),
OperandSize::S64,
OperandSize::S32,
);
} else {
self.asm
Expand Down Expand Up @@ -1333,11 +1333,11 @@ impl Masm for MacroAssembler {
}
let mask = Self::vpshuf_mask_for_64_bit_splats();
match src {
RegImm::Reg(src) => self.asm.xmm_vpshuf_rr(src, dst, mask, OperandSize::S64),
RegImm::Reg(src) => self.asm.xmm_vpshuf_rr(src, dst, mask, OperandSize::S32),
RegImm::Imm(imm) => {
let src = self.asm.add_constant(&imm.to_bytes());
self.asm
.xmm_vpshuf_mr(&src, dst, mask, OperandSize::S64, MemFlags::trusted());
.xmm_vpshuf_mr(&src, dst, mask, OperandSize::S32, MemFlags::trusted());
}
}
} else {
Expand Down Expand Up @@ -1582,6 +1582,6 @@ impl MacroAssembler {
// swapped and then the swapped bytes being copied.
// [d0, d1, d2, d3, d4, d5, d6, d7, ...] yields
// [d4, d5, d6, d7, d0, d1, d2, d3, d4, d5, d6, d7, d0, d1, d2, d3].
0b0100_0100
0b01_00_01_00
}
}
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