Merge pull request #3028 from cfallin/x86-legacy

cranelift-codegen: move old x86 and RISC-V backends to isa/legacy/.
bytecodealliance · Jun 24, 2021 · 7d47ba1 · 7d47ba1
2 parents 0c0a941 + 4b2723a
commit 7d47ba1
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Showing 17 changed files with 23 additions and 13 deletions.
diff --git a/cranelift/codegen/src/isa/legacy/mod.rs b/cranelift/codegen/src/isa/legacy/mod.rs
@@ -0,0 +1,12 @@
+//! Legacy ("old-style") backends that will be removed in the future.
+
+// N.B.: the old x86-64 backend (`x86`) and the new one (`x64`) are both
+// included whenever building with x86 support. The new backend is the default,
+// but the old can be requested with `BackendVariant::Legacy`. However, if this
+// crate is built with the `old-x86-backend` feature, then the old backend is
+// default instead.
+#[cfg(feature = "x86")]
+pub(crate) mod x86;
+
+#[cfg(feature = "riscv")]
+pub(crate) mod riscv;
diff --git a/cranelift/codegen/src/isa/riscv/abi.rs → ...elift/codegen/src/isa/legacy/riscv/abi.rs b/cranelift/codegen/src/isa/riscv/abi.rs → ...elift/codegen/src/isa/legacy/riscv/abi.rs
diff --git a/cranelift/codegen/src/isa/riscv/binemit.rs → ...t/codegen/src/isa/legacy/riscv/binemit.rs b/cranelift/codegen/src/isa/riscv/binemit.rs → ...t/codegen/src/isa/legacy/riscv/binemit.rs
diff --git a/...elift/codegen/src/isa/riscv/enc_tables.rs → ...odegen/src/isa/legacy/riscv/enc_tables.rs b/...elift/codegen/src/isa/riscv/enc_tables.rs → ...odegen/src/isa/legacy/riscv/enc_tables.rs
diff --git a/cranelift/codegen/src/isa/riscv/mod.rs → ...elift/codegen/src/isa/legacy/riscv/mod.rs b/cranelift/codegen/src/isa/riscv/mod.rs → ...elift/codegen/src/isa/legacy/riscv/mod.rs
diff --git a/cranelift/codegen/src/isa/riscv/registers.rs → ...codegen/src/isa/legacy/riscv/registers.rs b/cranelift/codegen/src/isa/riscv/registers.rs → ...codegen/src/isa/legacy/riscv/registers.rs
diff --git a/cranelift/codegen/src/isa/riscv/settings.rs → .../codegen/src/isa/legacy/riscv/settings.rs b/cranelift/codegen/src/isa/riscv/settings.rs → .../codegen/src/isa/legacy/riscv/settings.rs
diff --git a/cranelift/codegen/src/isa/x86/abi.rs → cranelift/codegen/src/isa/legacy/x86/abi.rs b/cranelift/codegen/src/isa/x86/abi.rs → cranelift/codegen/src/isa/legacy/x86/abi.rs
@@ -1,6 +1,6 @@
 //! x86 ABI implementation.
 
-use super::super::settings as shared_settings;
+use super::super::super::settings as shared_settings;
 use super::registers::{FPR, GPR, RU};
 use super::settings as isa_settings;
 use crate::abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};

diff --git a/cranelift/codegen/src/isa/x86/binemit.rs → ...ift/codegen/src/isa/legacy/x86/binemit.rs b/cranelift/codegen/src/isa/x86/binemit.rs → ...ift/codegen/src/isa/legacy/x86/binemit.rs
diff --git a/cranelift/codegen/src/isa/x86/enc_tables.rs → .../codegen/src/isa/legacy/x86/enc_tables.rs b/cranelift/codegen/src/isa/x86/enc_tables.rs → .../codegen/src/isa/legacy/x86/enc_tables.rs
diff --git a/cranelift/codegen/src/isa/x86/mod.rs → cranelift/codegen/src/isa/legacy/x86/mod.rs b/cranelift/codegen/src/isa/x86/mod.rs → cranelift/codegen/src/isa/legacy/x86/mod.rs
@@ -178,7 +178,7 @@ impl TargetIsa for Isa {
     fn create_unwind_info(
         &self,
         func: &ir::Function,
-    ) -> CodegenResult<Option<super::unwind::UnwindInfo>> {
+    ) -> CodegenResult<Option<super::super::unwind::UnwindInfo>> {
         abi::create_unwind_info(func, self)
     }
 

diff --git a/cranelift/codegen/src/isa/x86/registers.rs → ...t/codegen/src/isa/legacy/x86/registers.rs b/cranelift/codegen/src/isa/x86/registers.rs → ...t/codegen/src/isa/legacy/x86/registers.rs
diff --git a/cranelift/codegen/src/isa/x86/settings.rs → ...ft/codegen/src/isa/legacy/x86/settings.rs b/cranelift/codegen/src/isa/x86/settings.rs → ...ft/codegen/src/isa/legacy/x86/settings.rs
diff --git a/cranelift/codegen/src/isa/x86/unwind.rs → ...lift/codegen/src/isa/legacy/x86/unwind.rs b/cranelift/codegen/src/isa/x86/unwind.rs → ...lift/codegen/src/isa/legacy/x86/unwind.rs
diff --git a/...ift/codegen/src/isa/x86/unwind/systemv.rs → ...egen/src/isa/legacy/x86/unwind/systemv.rs b/...ift/codegen/src/isa/x86/unwind/systemv.rs → ...egen/src/isa/legacy/x86/unwind/systemv.rs
diff --git a/...lift/codegen/src/isa/x86/unwind/winx64.rs → ...degen/src/isa/legacy/x86/unwind/winx64.rs b/...lift/codegen/src/isa/x86/unwind/winx64.rs → ...degen/src/isa/legacy/x86/unwind/winx64.rs
diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs
@@ -70,17 +70,6 @@ use core::fmt::{Debug, Formatter};
 use core::hash::Hasher;
 use target_lexicon::{triple, Architecture, OperatingSystem, PointerWidth, Triple};
 
-#[cfg(feature = "riscv")]
-mod riscv;
-
-// N.B.: the old x86-64 backend (`x86`) and the new one (`x64`) are both
-// included whenever building with x86 support. The new backend is the default,
-// but the old can be requested with `BackendVariant::Legacy`. However, if this
-// crate is built with the `old-x86-backend` feature, then the old backend is
-// default instead.
-#[cfg(feature = "x86")]
-mod x86;
-
 // This module is made public here for benchmarking purposes. No guarantees are
 // made regarding API stability.
 #[cfg(feature = "x86")]
@@ -95,6 +84,15 @@ pub(crate) mod aarch64;
 #[cfg(feature = "s390x")]
 mod s390x;
 
+#[cfg(any(feature = "x86", feature = "riscv"))]
+mod legacy;
+
+#[cfg(feature = "x86")]
+use legacy::x86;
+
+#[cfg(feature = "riscv")]
+use legacy::riscv;
+
 pub mod unwind;
 
 mod call_conv;