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Force STK500 EEPROM paged r/w for bootloaders #1602
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Tests should check |
I can't say I'm having any issues with optiboot_x (from the MegaCoreX repo) when using git main and -carduino:
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With the combination of The purpose of this patch is to improve the "page_size=1" part. Currently this applies to Dx AT pack products. Please note that official Optiboot only supports up to "optiboot_x", i.e. NVMCTRL version 0. (Subsequent new product support proposals were rejected. Based on AT pack classification, only Mega/Tiny AT packs are supported) |
Optiboot_dx supports AVR DA/DB/DD family. That is what we tested within avrdude project. For optiboot_x, the following two implementations are tested within avdude project. If your implementation deviates from the above, then you may have to come out with patches which do not break the existing implementations. |
Of course I know. I've been keeping an eye on all its variants (forked from Optiboot) and doing comparative testing as well. Additionally, I may be able to add an "unnamed" STK500 v1 compatible boot that I maintain to that list... All NVMCTRL version 0 products (for Mega/Tiny AT pack) All NVMCTRL version 2 and 4 products (for Dx AT pack) All NVMCTRL version 3 and 5 products (for Ex AT pack) FLASH/EEPROM rewrite functionality is no different from other variants. It maintains complete upward compatibility and has been tested as much as possible with "AVRDUDE 6.3 - 7.3 (main)". The difference from other variants is that multiple chips with different signatures are shared in one binary, all binaries are EEPROM writable, changeable to hardware level RS485 and single wire serial, APPCODE There is an update snippet and CRCSCAN is supported. I'm also working on starting a minimal protocol for 1/2 wire communication using hardware auto-baud (similar to UPDI), but it's not related to AVRDUDE or urboot yet. |
Older PRs and test reports for your reference: |
Thanks for pointing me to the old link. Please excuse me, but let me summarize some of the main points of writing boot code with the PM_UPDI chip. Regarding the 64KiB/128KiB difference for the AVR_DA/DB family, we can infer that the current Intel-HEX output by avrdude tells it to generate only one
On the other hand, the boot method of switching his PGMEM bank with his FLMAP (LD/ST only) in NVMCTRL_CTRLB is harmful (silicon errata) at least for AVR128DA. There are few benefits to using FLMAP other than being able to code only in C/C++. The ELPM/SPM method is linear up to 64KiB. tiny/megaAVR does not have ELPM/SPM. Write the flash using normal LD/ST. So boot code has a habit of adding The 24bit MSB is important in UPDI, but is ignored when writing to RAMPZ within BOOTAPP. Other than the LSB, it is always fixed at zero, so there is no harm done. |
Just want to summarize your findings in Discussion #1473:
Please confirm that my understandings are correct. And based on your tests with AVR32DA32, this PR #1602 fixed the issue above issue with optiboot_dx. |
I can confirm that there is no issue with git main for ATmega4808/4809 using optiboox_x from MegaCore. I will test with optiboot_dx later. Example for Arduino Nano Every (using ATmega4809).
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No regression from this PR either.
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The problem of not being able to write to EEPROM in Arduino Nano Every + interactive mode can be resolved by applying the following patch to
diff --git a/src/jtagmkII.c b/src/jtagmkII.c
index 0cadeba7..0afb50e0 100644
--- a/src/jtagmkII.c
+++ b/src/jtagmkII.c
@@ -1929,7 +1929,7 @@ static int jtagmkII_paged_write(const PROGRAMMER *pgm, const AVRPART *p, const A
free(cmd);
return n_bytes;
}
- cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM: MTYPE_EEPROM_PAGE;
+ cmd[1] = p->prog_modes & (PM_PDI | PM_UPDI)? MTYPE_EEPROM_XMEGA: MTYPE_EEPROM_PAGE;
PDATA(pgm)->eeprom_pageaddr = (unsigned long)-1L;
} else if (mem_is_userrow(m)) {
cmd[1] = MTYPE_USERSIG;
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Thanks for this patch @askn37! Please could you submit an independent PR, so the team can test whether this change results in a regression for other programmers. |
Fixes failing terminal r/w of UPDI EEPROM for
-c arduino
and-c urclock
. See discussion