Addressing review comments.

anthonycanino · Mar 28, 2023 · 95d12db · 95d12db
1 parent d072495
commit 95d12db
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Showing 5 changed files with 77 additions and 93 deletions.
diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp
@@ -34,9 +34,19 @@ bool emitter::IsSSEOrAVXInstruction(instruction ins)
     return (ins >= INS_FIRST_SSE_INSTRUCTION) && (ins <= INS_LAST_AVX_INSTRUCTION);
 }
 
+//------------------------------------------------------------------------
+// IsKInstruction: Does this instruction require K register.
+//
+// Arguments:
+//    ins - The instruction to check.
+//
+// Returns:
+//    `true` if this instruction require K register.
+//
 bool emitter::IsKInstruction(instruction ins)
 {
-    return (ins >= INS_FIRST_K_INSTRUCTION) && (ins <= INS_LAST_K_INSTRUCTION);
+    insFlags flags = CodeGenInterface::instInfo[ins];
+    return (flags & KInstruction) != 0;
 }
 
 //------------------------------------------------------------------------

diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -20386,9 +20386,7 @@ GenTree* Compiler::gtNewSimdCmpOpNode(genTreeOps  op,
             }
             else if (simdSize == 64)
             {
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512F));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512BW));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512DQ));
+                assert(IsBaselineVector512IsaSupportedDebugOnly());
                 intrinsic = NI_AVX512F_CompareEqualSpecial;
             }
             else if (simdBaseType == TYP_FLOAT)
@@ -21021,9 +21019,7 @@ GenTree* Compiler::gtNewSimdCmpOpAllNode(genTreeOps  op,
         {
             if (simdSize == 64)
             {
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512F));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512BW));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512DQ));
+                assert(IsBaselineVector512IsaSupportedDebugOnly());
                 intrinsic = NI_Vector512_op_Equality;
             }
             else if (simdSize == 32)
@@ -21179,9 +21175,7 @@ GenTree* Compiler::gtNewSimdCmpOpAnyNode(genTreeOps  op,
             }
             else if (simdSize == 64)
             {
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512F));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512BW));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512DQ));
+                assert(IsBaselineVector512IsaSupportedDebugOnly());
                 intrinsic = NI_Vector512_op_Inequality;
             }
             else
@@ -21209,9 +21203,7 @@ GenTree* Compiler::gtNewSimdCmpOpAnyNode(genTreeOps  op,
         {
             if (simdSize == 64)
             {
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512F));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512BW));
-                assert(compIsaSupportedDebugOnly(InstructionSet_AVX512DQ));
+                assert(IsBaselineVector512IsaSupportedDebugOnly());
                 intrinsic = NI_Vector512_op_Inequality;
             }
             else if (simdSize == 32)

diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp
@@ -1305,36 +1305,29 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic        intrinsic,
         case NI_Vector512_Equals:
         {
             assert(sig->numArgs == 2);
+            assert(IsBaselineVector512IsaSupportedDebugOnly());
 
-            if (IsBaselineVector512IsaSupported())
-            {
-                var_types simdType = getSIMDTypeForSize(simdSize);
-
-                op2 = impSIMDPopStack(simdType);
-                op1 = impSIMDPopStack(simdType);
-
-                retNode = gtNewSimdCmpOpNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
+            var_types simdType = getSIMDTypeForSize(simdSize);
+            op2 = impSIMDPopStack(simdType);
+            op1 = impSIMDPopStack(simdType);
+            retNode = gtNewSimdCmpOpNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
                                              /* isSimdAsHWIntrinsic */ false);
-            }
             break;
         }
 
         case NI_Vector512_EqualsAll:
         case NI_Vector512_op_Equality:
         {
             assert(sig->numArgs == 2);
+            assert(IsBaselineVector512IsaSupportedDebugOnly());
 
-            if (IsBaselineVector512IsaSupported())
-            {
-                var_types simdType = getSIMDTypeForSize(simdSize);
-
-                op2 = impSIMDPopStack(simdType);
-                op1 = impSIMDPopStack(simdType);
+            var_types simdType = getSIMDTypeForSize(simdSize);
 
-                retNode = gtNewSimdCmpOpAllNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
-                                                /* isSimdAsHWIntrinsic */ false);
-            }
+            op2 = impSIMDPopStack(simdType);
+            op1 = impSIMDPopStack(simdType);
 
+            retNode = gtNewSimdCmpOpAllNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
+                                            /* isSimdAsHWIntrinsic */ false);
             break;
         }
 
@@ -1362,17 +1355,15 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic        intrinsic,
         {
             assert(sig->numArgs == 2);
             assert(simdSize == 64);
+            assert(IsBaselineVector512IsaSupportedDebugOnly());
 
-            if (IsBaselineVector512IsaSupported())
-            {
-                var_types simdType = getSIMDTypeForSize(simdSize);
+            var_types simdType = getSIMDTypeForSize(simdSize);
 
-                op2 = impSIMDPopStack(simdType);
-                op1 = impSIMDPopStack(simdType);
+            op2 = impSIMDPopStack(simdType);
+            op1 = impSIMDPopStack(simdType);
 
-                retNode = gtNewSimdCmpOpAnyNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
-                                                /* isSimdAsHWIntrinsic */ false);
-            }
+            retNode = gtNewSimdCmpOpAnyNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
+                                            /* isSimdAsHWIntrinsic */ false);
             break;
         }
 

diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h
@@ -171,6 +171,8 @@ enum insFlags : uint64_t
     Encoding_VEX   = 1ULL << 37,
     Encoding_EVEX  = 1ULL << 38,
 
+    KInstruction = 1ULL << 39,
+
     // Listed above so it is "inline" with the other Resets_* flags
     // Resets_ZF = 1ULL << 39,