guest-programs/riscv-tests: Add risc-v Zbb instruction set tests

Signed-off-by: Aman <[email protected]>

crates/polkavm/src/tests_riscv.rs

@@ -111,6 +111,42 @@ riscv_test!(riscv_unoptimized_rv32um_rem, "../../../guest-programs/riscv-tests/o
 riscv_test!(riscv_optimized_rv32um_rem, "../../../guest-programs/riscv-tests/output/rv32um/rem.elf", S0, true);
 riscv_test!(riscv_unoptimized_rv32um_remu, "../../../guest-programs/riscv-tests/output/rv32um/remu.elf", S0, false);
 riscv_test!(riscv_optimized_rv32um_remu, "../../../guest-programs/riscv-tests/output/rv32um/remu.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_andn, "../../../guest-programs/riscv-tests/output/rv32uzbb/andn.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_andn, "../../../guest-programs/riscv-tests/output/rv32uzbb/andn.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_clz, "../../../guest-programs/riscv-tests/output/rv32uzbb/clz.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_clz, "../../../guest-programs/riscv-tests/output/rv32uzbb/clz.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_cpop, "../../../guest-programs/riscv-tests/output/rv32uzbb/cpop.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_cpop, "../../../guest-programs/riscv-tests/output/rv32uzbb/cpop.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_ctz, "../../../guest-programs/riscv-tests/output/rv32uzbb/ctz.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_ctz, "../../../guest-programs/riscv-tests/output/rv32uzbb/ctz.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_max, "../../../guest-programs/riscv-tests/output/rv32uzbb/max.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_max, "../../../guest-programs/riscv-tests/output/rv32uzbb/max.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_maxu, "../../../guest-programs/riscv-tests/output/rv32uzbb/maxu.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_maxu, "../../../guest-programs/riscv-tests/output/rv32uzbb/maxu.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_min, "../../../guest-programs/riscv-tests/output/rv32uzbb/min.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_min, "../../../guest-programs/riscv-tests/output/rv32uzbb/min.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_minu, "../../../guest-programs/riscv-tests/output/rv32uzbb/minu.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_minu, "../../../guest-programs/riscv-tests/output/rv32uzbb/minu.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_orc_b, "../../../guest-programs/riscv-tests/output/rv32uzbb/orc_b.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_orc_b, "../../../guest-programs/riscv-tests/output/rv32uzbb/orc_b.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_orn, "../../../guest-programs/riscv-tests/output/rv32uzbb/orn.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_orn, "../../../guest-programs/riscv-tests/output/rv32uzbb/orn.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_rev8, "../../../guest-programs/riscv-tests/output/rv32uzbb/rev8.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_rev8, "../../../guest-programs/riscv-tests/output/rv32uzbb/rev8.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_rol, "../../../guest-programs/riscv-tests/output/rv32uzbb/rol.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_rol, "../../../guest-programs/riscv-tests/output/rv32uzbb/rol.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_ror, "../../../guest-programs/riscv-tests/output/rv32uzbb/ror.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_ror, "../../../guest-programs/riscv-tests/output/rv32uzbb/ror.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_rori, "../../../guest-programs/riscv-tests/output/rv32uzbb/rori.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_rori, "../../../guest-programs/riscv-tests/output/rv32uzbb/rori.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_sext_b, "../../../guest-programs/riscv-tests/output/rv32uzbb/sext_b.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_sext_b, "../../../guest-programs/riscv-tests/output/rv32uzbb/sext_b.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_sext_h, "../../../guest-programs/riscv-tests/output/rv32uzbb/sext_h.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_sext_h, "../../../guest-programs/riscv-tests/output/rv32uzbb/sext_h.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_xnor, "../../../guest-programs/riscv-tests/output/rv32uzbb/xnor.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_xnor, "../../../guest-programs/riscv-tests/output/rv32uzbb/xnor.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv32uzbb_zext_h, "../../../guest-programs/riscv-tests/output/rv32uzbb/zext_h.elf", S0, false);
+riscv_test!(riscv_optimized_rv32uzbb_zext_h, "../../../guest-programs/riscv-tests/output/rv32uzbb/zext_h.elf", S0, true);
 riscv_test!(riscv_unoptimized_rv64ua_amoadd_d, "../../../guest-programs/riscv-tests/output/rv64ua/amoadd_d.elf", S0, false);
 riscv_test!(riscv_optimized_rv64ua_amoadd_d, "../../../guest-programs/riscv-tests/output/rv64ua/amoadd_d.elf", S0, true);
 riscv_test!(riscv_unoptimized_rv64ua_amoadd_w, "../../../guest-programs/riscv-tests/output/rv64ua/amoadd_w.elf", S0, false);
@@ -274,4 +310,52 @@ riscv_test!(riscv_optimized_rv64um_remu, "../../../guest-programs/riscv-tests/ou
 riscv_test!(riscv_unoptimized_rv64um_remuw, "../../../guest-programs/riscv-tests/output/rv64um/remuw.elf", S0, false);
 riscv_test!(riscv_optimized_rv64um_remuw, "../../../guest-programs/riscv-tests/output/rv64um/remuw.elf", S0, true);
 riscv_test!(riscv_unoptimized_rv64um_remw, "../../../guest-programs/riscv-tests/output/rv64um/remw.elf", S0, false);
-riscv_test!(riscv_optimized_rv64um_remw, "../../../guest-programs/riscv-tests/output/rv64um/remw.elf", S0, true);
+riscv_test!(riscv_optimized_rv64um_remw, "../../../guest-programs/riscv-tests/output/rv64um/remw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_andn, "../../../guest-programs/riscv-tests/output/rv64uzbb/andn.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_andn, "../../../guest-programs/riscv-tests/output/rv64uzbb/andn.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_clz, "../../../guest-programs/riscv-tests/output/rv64uzbb/clz.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_clz, "../../../guest-programs/riscv-tests/output/rv64uzbb/clz.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_clzw, "../../../guest-programs/riscv-tests/output/rv64uzbb/clzw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_clzw, "../../../guest-programs/riscv-tests/output/rv64uzbb/clzw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_cpop, "../../../guest-programs/riscv-tests/output/rv64uzbb/cpop.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_cpop, "../../../guest-programs/riscv-tests/output/rv64uzbb/cpop.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_cpopw, "../../../guest-programs/riscv-tests/output/rv64uzbb/cpopw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_cpopw, "../../../guest-programs/riscv-tests/output/rv64uzbb/cpopw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_ctz, "../../../guest-programs/riscv-tests/output/rv64uzbb/ctz.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_ctz, "../../../guest-programs/riscv-tests/output/rv64uzbb/ctz.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_ctzw, "../../../guest-programs/riscv-tests/output/rv64uzbb/ctzw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_ctzw, "../../../guest-programs/riscv-tests/output/rv64uzbb/ctzw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_max, "../../../guest-programs/riscv-tests/output/rv64uzbb/max.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_max, "../../../guest-programs/riscv-tests/output/rv64uzbb/max.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_maxu, "../../../guest-programs/riscv-tests/output/rv64uzbb/maxu.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_maxu, "../../../guest-programs/riscv-tests/output/rv64uzbb/maxu.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_min, "../../../guest-programs/riscv-tests/output/rv64uzbb/min.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_min, "../../../guest-programs/riscv-tests/output/rv64uzbb/min.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_minu, "../../../guest-programs/riscv-tests/output/rv64uzbb/minu.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_minu, "../../../guest-programs/riscv-tests/output/rv64uzbb/minu.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_orc_b, "../../../guest-programs/riscv-tests/output/rv64uzbb/orc_b.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_orc_b, "../../../guest-programs/riscv-tests/output/rv64uzbb/orc_b.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_orn, "../../../guest-programs/riscv-tests/output/rv64uzbb/orn.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_orn, "../../../guest-programs/riscv-tests/output/rv64uzbb/orn.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_rev8, "../../../guest-programs/riscv-tests/output/rv64uzbb/rev8.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_rev8, "../../../guest-programs/riscv-tests/output/rv64uzbb/rev8.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_rol, "../../../guest-programs/riscv-tests/output/rv64uzbb/rol.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_rol, "../../../guest-programs/riscv-tests/output/rv64uzbb/rol.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_rolw, "../../../guest-programs/riscv-tests/output/rv64uzbb/rolw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_rolw, "../../../guest-programs/riscv-tests/output/rv64uzbb/rolw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_ror, "../../../guest-programs/riscv-tests/output/rv64uzbb/ror.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_ror, "../../../guest-programs/riscv-tests/output/rv64uzbb/ror.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_rori, "../../../guest-programs/riscv-tests/output/rv64uzbb/rori.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_rori, "../../../guest-programs/riscv-tests/output/rv64uzbb/rori.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_roriw, "../../../guest-programs/riscv-tests/output/rv64uzbb/roriw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_roriw, "../../../guest-programs/riscv-tests/output/rv64uzbb/roriw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_rorw, "../../../guest-programs/riscv-tests/output/rv64uzbb/rorw.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_rorw, "../../../guest-programs/riscv-tests/output/rv64uzbb/rorw.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_sext_b, "../../../guest-programs/riscv-tests/output/rv64uzbb/sext_b.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_sext_b, "../../../guest-programs/riscv-tests/output/rv64uzbb/sext_b.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_sext_h, "../../../guest-programs/riscv-tests/output/rv64uzbb/sext_h.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_sext_h, "../../../guest-programs/riscv-tests/output/rv64uzbb/sext_h.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_xnor, "../../../guest-programs/riscv-tests/output/rv64uzbb/xnor.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_xnor, "../../../guest-programs/riscv-tests/output/rv64uzbb/xnor.elf", S0, true);
+riscv_test!(riscv_unoptimized_rv64uzbb_zext_h, "../../../guest-programs/riscv-tests/output/rv64uzbb/zext_h.elf", S0, false);
+riscv_test!(riscv_optimized_rv64uzbb_zext_h, "../../../guest-programs/riscv-tests/output/rv64uzbb/zext_h.elf", S0, true);

guest-programs/riscv-tests/build.rb

@@ -35,7 +35,7 @@
         mabi = "ilp32"
     end
 
-    march += "ima_zifencei"
+    march += "ima_zifencei_zbb"
 
     FileUtils.mkdir_p File.dirname(output_path)
     FileUtils.mkdir_p File.dirname(raw_output_path)

guest-programs/riscv-tests/tests/rv32uzbb/Makefrag

@@ -0,0 +1,26 @@
+#=======================================================================
+# Makefrag for rv32uzbb tests
+#-----------------------------------------------------------------------
+
+rv32uzbb_sc_tests = \
+	andn \
+	clz \
+	cpop \
+	ctz \
+	max maxu \
+	min minu \
+	orc_b \
+	orn \
+	rev8 \
+	rol \
+	ror \
+	rori \
+	sext_b sext_h \
+	xnor \
+	zext_h \
+
+rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests))
+rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests))
+rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests))
+
+spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests)

guest-programs/riscv-tests/tests/rv32uzbb/andn.S

@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uzbb/andn.S"

guest-programs/riscv-tests/tests/rv32uzbb/clz.S

@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# clz.S
+#-----------------------------------------------------------------------------
+#
+# Test clz instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_R_OP( 2,  clz, 32, 0x00000000);
+  TEST_R_OP( 3,  clz, 31, 0x00000001);
+  TEST_R_OP( 4,  clz, 30, 0x00000003);
+
+  TEST_R_OP( 5,  clz, 0, 0xffff8000 );
+  TEST_R_OP( 6,  clz, 8, 0x00800000 );
+  TEST_R_OP( 7,  clz, 0, 0xffff8000 );
+
+  TEST_R_OP( 8,  clz, 17, 0x00007fff);
+  TEST_R_OP( 9,  clz, 1, 0x7fffffff);
+  TEST_R_OP( 10, clz, 13, 0x0007ffff );
+
+  TEST_R_OP( 11, clz, 0, 0x80000000);
+  TEST_R_OP( 12, clz, 3, 0x121f5000);
+
+  TEST_R_OP( 13, clz, 5, 0x04000000);
+  TEST_R_OP( 14, clz, 28, 0x0000000e);
+  TEST_R_OP( 15, clz, 2, 0x20401341);
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13);
+  TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11);
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13);
+  TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19);
+  TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34);
+
+  #-------------------------------------------------------------
+  # Other tests
+  #-------------------------------------------------------------
+
+
+  TEST_R_OP( 21, clz, 5, 0x070f8000 );
+  TEST_R_OP( 22, clz, 4, 0x08008000 );
+  TEST_R_OP( 23, clz, 3, 0x18008000 );
+
+  TEST_R_OP( 24, clz, 17, 0x00007fff);
+  TEST_R_OP( 25, clz, 1, 0x7fffffff);
+  TEST_R_OP( 26, clz, 13, 0x0007ffff);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

guest-programs/riscv-tests/tests/rv32uzbb/cpop.S

@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# cpop.S
+#-----------------------------------------------------------------------------
+#
+# Test cpop instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_R_OP( 2,  cpop, 0, 0x00000000);
+  TEST_R_OP( 3,  cpop, 1, 0x00000001);
+  TEST_R_OP( 4,  cpop, 2, 0x00000003);
+
+  TEST_R_OP( 5,  cpop, 17, 0xffff8000 );
+  TEST_R_OP( 6,  cpop, 1, 0x00800000 );
+  TEST_R_OP( 7,  cpop, 18, 0xffff6000 );
+
+  TEST_R_OP( 8,  cpop, 15, 0x00007fff);
+  TEST_R_OP( 9,  cpop, 31, 0x7fffffff);
+  TEST_R_OP( 10, cpop, 19, 0x0007ffff );
+
+  TEST_R_OP( 11, cpop, 1, 0x80000000);
+  TEST_R_OP( 12, cpop, 9, 0x121f5000);
+
+  TEST_R_OP( 13, cpop, 0, 0x00000000);
+  TEST_R_OP( 14, cpop, 3, 0x0000000e);
+  TEST_R_OP( 15, cpop, 7, 0x20401341);
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13);
+  TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11);
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13);
+  TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19);
+  TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34);
+
+  #-------------------------------------------------------------
+  # Other tests
+  #-------------------------------------------------------------
+
+  TEST_R_OP( 21,  cpop, 8, 0x007f8000 );
+  TEST_R_OP( 22,  cpop, 2, 0x00808000 );
+  TEST_R_OP( 23,  cpop, 3, 0x01808000 );
+
+  TEST_R_OP( 24,  cpop, 17, 0x30007fff);
+  TEST_R_OP( 25,  cpop, 30, 0x77ffffff);
+  TEST_R_OP( 26,  cpop, 19, 0x0007ffff);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

guest-programs/riscv-tests/tests/rv32uzbb/ctz.S

@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ctz.S
+#-----------------------------------------------------------------------------
+#
+# Test ctz instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_R_OP( 2,  ctz, 32, 0x00000000);
+  TEST_R_OP( 3,  ctz, 0, 0x00000001);
+  TEST_R_OP( 4,  ctz, 0, 0x00000003);
+
+  TEST_R_OP( 5,  ctz, 15, 0xffff8000 );
+  TEST_R_OP( 6,  ctz, 23, 0x00800000 );
+  TEST_R_OP( 7,  ctz, 15, 0xffff8000 );
+
+  TEST_R_OP( 8,  ctz, 0, 0x00007fff);
+  TEST_R_OP( 9,  ctz, 0, 0x7fffffff);
+  TEST_R_OP( 10, ctz, 0, 0x0007ffff );
+
+  TEST_R_OP( 11, ctz, 31, 0x80000000);
+  TEST_R_OP( 12, ctz, 12, 0x121f5000);
+
+  TEST_R_OP( 13, ctz, 30, 0xc0000000);
+  TEST_R_OP( 14, ctz, 1, 0x0000000e);
+  TEST_R_OP( 15, ctz, 0, 0x20401341);
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13);
+  TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11);
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13);
+  TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19);
+  TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34);
+
+  #-------------------------------------------------------------
+  # Other tests
+  #-------------------------------------------------------------
+
+  TEST_R_OP( 21,  ctz, 15, 0x007f8000 );
+  TEST_R_OP( 22,  ctz, 15, 0x00808000 );
+  TEST_R_OP( 23,  ctz, 12, 0x01809000 );
+
+  TEST_R_OP( 24,  ctz, 0, 0x00007fff);
+  TEST_R_OP( 25,  ctz, 0, 0x7fffffff);
+  TEST_R_OP( 26,  ctz, 0, 0x0007ffff);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

guest-programs/riscv-tests/tests/rv32uzbb/max.S

@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uzbb/max.S"

guest-programs/riscv-tests/tests/rv32uzbb/maxu.S

@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uzbb/maxu.S"

guest-programs/riscv-tests/tests/rv32uzbb/min.S

@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uzbb/min.S"