fix(Soc, CoupledL2): correct port width of CHI Issue C (OpenXiangShan…

…#4290)
ZTHKaiYuan · Feb 19, 2025 · aad6182 · aad6182
1 parent 075d493
commit aad6182
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/coupledL2 b/coupledL2
diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala
@@ -77,7 +77,7 @@ case class SoCParameters
   XSTopPrefix: Option[String] = None,
   NodeIDWidthList: Map[String, Int] = Map(
     "B" -> 7,
-    "C" -> 7,
+    "C" -> 9,
     "E.b" -> 11
   ),
   NumHart: Int = 64,
+2 −0		src/main/scala/coupledL2/Common.scala
+2 −2		src/main/scala/coupledL2/SinkC.scala
+14 −1		src/main/scala/coupledL2/tl2chi/MSHR.scala
+8 −5		src/main/scala/coupledL2/tl2chi/MainPipe.scala
+16 −15		src/main/scala/coupledL2/tl2chi/RXDAT.scala
+1 −1		src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
+5 −2		src/main/scala/coupledL2/tl2chi/chi/Message.scala