style(Bundles): move bundles to Bundles.scala (OpenXiangShan#4247)

ZTHKaiYuan · Feb 8, 2025 · 9e12e8e · 9e12e8e
1 parent 5f84a7f
commit 9e12e8e
Show file tree

Hide file tree

Showing 35 changed files with 657 additions and 591 deletions.
diff --git a/src/main/scala/xiangshan/backend/issue/EnqEntry.scala b/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
@@ -11,7 +11,8 @@ import xiangshan.backend.fu.FuType
 import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.rob.RobPtr
 import xiangshan.backend.issue.EntryBundles._
-import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
+import xiangshan.mem.{SqPtr, LqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 
 class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
@@ -92,7 +93,7 @@ class EnqEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams
                                                     (enqDelayOut1.srcWakeUpByIQ(i).asBool && enqDelay1IsWakeupByMemIQ)   -> DataSource.bypass2,
                                                     (enqDelayOut2.srcWakeUpByIQ(i).asBool && !enqDelay2IsWakeupByMemIQ)  -> DataSource.bypass2,
                                                  ))
-      enqDelayExuSources.get(i).value         := Mux(enqDelay1WakeUpValid, 
+      enqDelayExuSources.get(i).value         := Mux(enqDelay1WakeUpValid,
                                                       ExuSource().fromExuOH(params, Mux1H(enqDelay1WakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)))),
                                                       ExuSource().fromExuOH(params, Mux1H(enqDelay2WakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)))))
     }
@@ -101,7 +102,7 @@ class EnqEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams
                                                     enqDelayOut1.srcWakeUpByIQ(i).asBool                                 -> DataSource.bypass,
                                                     (enqDelayOut2.srcWakeUpByIQ(i).asBool && enqDelay2IsWakeupByVfIQ)    -> DataSource.bypass2,
                                                  ))
-      enqDelayExuSources.get(i).value         := Mux(enqDelay1WakeUpValid, 
+      enqDelayExuSources.get(i).value         := Mux(enqDelay1WakeUpValid,
                                                       ExuSource().fromExuOH(params, Mux1H(enqDelay1WakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)))),
                                                       ExuSource().fromExuOH(params, Mux1H(enqDelay2WakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)))))
     }
@@ -175,4 +176,4 @@ object EnqEntry {
       case _ => null
     }
   }
-}
+}
diff --git a/src/main/scala/xiangshan/backend/issue/Entries.scala b/src/main/scala/xiangshan/backend/issue/Entries.scala
@@ -13,8 +13,9 @@ import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.fu.vector.Utils.NOnes
 import xiangshan.backend.rob.RobPtr
-import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
 import xiangshan.backend.issue.EntryBundles._
+import xiangshan.mem.{LqPtr, SqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
   override def desiredName: String = params.getEntryName

diff --git a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
@@ -12,7 +12,8 @@ import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.fu.vector.Bundles.NumLsElem
 import xiangshan.backend.rob.RobPtr
-import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
+import xiangshan.mem.{LqPtr, SqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 object EntryBundles extends HasCircularQueuePtrHelper {
 
@@ -174,11 +175,11 @@ object EntryBundles extends HasCircularQueuePtrHelper {
     common.flushed            := status.robIdx.needFlush(commonIn.flush)
     common.deqSuccess         := (if (params.isVecMemIQ) status.issued else true.B) &&
       commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR
-    common.srcWakeupByWB      := commonIn.wakeUpFromWB.map{ bundle => 
+    common.srcWakeupByWB      := commonIn.wakeUpFromWB.map{ bundle =>
                                     val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)
                                     if (params.numRegSrc == 5) {
-                                      bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 
-                                      bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 
+                                      bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+
+                                      bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+
                                       bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid)
                                     }
                                     else
@@ -202,7 +203,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
     }
     if (params.numRegSrc == 5) {
       // only when numRegSrc == 5 need vl
-      val wakeUpFromVl = VecInit(commonIn.wakeUpFromWB.map{ bundle => 
+      val wakeUpFromVl = VecInit(commonIn.wakeUpFromWB.map{ bundle =>
         val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)
         bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid)
       })
@@ -233,8 +234,8 @@ object EntryBundles extends HasCircularQueuePtrHelper {
     val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
       val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)
       if (params.numRegSrc == 5) {
-        bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 
-        bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 
+        bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+
+        bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+
         bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4))
       }
       else
@@ -521,7 +522,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
 
   def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = {
     enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
-      wakeup := enqDelayIn.wakeUpFromWB.map{ x => 
+      wakeup := enqDelayIn.wakeUpFromWB.map{ x =>
         if (i == 3)
           x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid)
         else if (i == 4)
@@ -535,8 +536,8 @@ object EntryBundles extends HasCircularQueuePtrHelper {
       val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x =>
         val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)
         if (params.numRegSrc == 5) {
-          x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 
-          x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 
+          x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+
+          x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+
           x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4))
         }
         else

diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
@@ -12,10 +12,11 @@ import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
 import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.fu.{FuConfig, FuType}
-import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
 import xiangshan.backend.rob.RobPtr
 import xiangshan.backend.datapath.NewPipelineConnect
 import xiangshan.backend.fu.vector.Bundles.VSew
+import xiangshan.mem.{LqPtr, SqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
   override def shouldBeInlined: Boolean = false
@@ -304,8 +305,8 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
         enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
         enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
         enq.bits.status.srcStatus(j).srcState                   := (if (j < 3) {
-                                                                      Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 
-                                                                          SrcState.rdy, 
+                                                                      Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
+                                                                          SrcState.rdy,
                                                                           s0_enqBits(enqIdx).srcState(j))
                                                                     } else {
                                                                       s0_enqBits(enqIdx).srcState(j)
@@ -1177,7 +1178,7 @@ class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Paramete
       enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
       // MemAddrIQ also handle vector insts
       enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
-    
+
       val isFirstLoad           = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get
       val isVleff               = s0_enqBits(i).vpu.isVleff
       enqData.blocked          := !isFirstLoad && isVleff

diff --git a/src/main/scala/xiangshan/backend/issue/OthersEntry.scala b/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
@@ -11,7 +11,8 @@ import xiangshan.backend.fu.FuType
 import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.rob.RobPtr
 import xiangshan.backend.issue.EntryBundles._
-import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
+import xiangshan.mem.{SqPtr, LqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 
 class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
@@ -79,4 +80,4 @@ object OthersEntry {
       case _ => null
     }
   }
-}
+}
diff --git a/src/main/scala/xiangshan/backend/issue/Scheduler.scala b/src/main/scala/xiangshan/backend/issue/Scheduler.scala
@@ -12,10 +12,11 @@ import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.WbConfig._
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.regfile.RfWritePortWithConfig
-import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr}
 import xiangshan.backend.datapath.WbConfig.V0WB
 import xiangshan.backend.regfile.VlPregParams
 import xiangshan.backend.regcache.RegCacheTagTable
+import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, SqPtr, LqPtr}
+import xiangshan.mem.Bundles.MemWaitUpdateReq
 
 sealed trait SchedulerType
 
@@ -306,10 +307,10 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
 
   // Connect each replace RCIdx to IQ
   if (params.needWriteRegCache) {
-    val iqReplaceRCIdxVec = issueQueues.filter(_.params.needWriteRegCache).flatMap{ iq => 
+    val iqReplaceRCIdxVec = issueQueues.filter(_.params.needWriteRegCache).flatMap{ iq =>
       iq.params.allExuParams.zip(iq.io.replaceRCIdx.get).filter(_._1.needWriteRegCache).map(_._2)
     }
-    iqReplaceRCIdxVec.zip(io.fromDataPath.replaceRCIdx.get).foreach{ case (iq, in) => 
+    iqReplaceRCIdxVec.zip(io.fromDataPath.replaceRCIdx.get).foreach{ case (iq, in) =>
       iq := in
     }
 

diff --git a/src/main/scala/xiangshan/cache/dcache/Uncache.scala b/src/main/scala/xiangshan/cache/dcache/Uncache.scala
@@ -16,18 +16,17 @@
 
 package xiangshan.cache
 
+import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
-import org.chipsalliance.cde.config.Parameters
 import utils._
 import utility._
-import xiangshan._
-import xiangshan.mem._
-import coupledL2.MemBackTypeMM
-import coupledL2.MemPageTypeNC
 import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
 import freechips.rocketchip.tilelink.{TLArbiter, TLBundleA, TLBundleD, TLClientNode, TLEdgeOut, TLMasterParameters, TLMasterPortParameters}
-import coupledL2.{MemBackTypeMMField, MemPageTypeNCField}
+import xiangshan._
+import xiangshan.mem._
+import xiangshan.mem.Bundles._
+import coupledL2.{MemBackTypeMM, MemBackTypeMMField, MemPageTypeNC, MemPageTypeNCField}
 
 trait HasUncacheBufferParameters extends HasXSParameter with HasDCacheParameters {
 
@@ -134,7 +133,7 @@ class UncacheEntryState(implicit p: Parameters) extends DCacheBundle {
   val inflight = Bool() // uncache -> L2
   val waitSame = Bool()
   val waitReturn = Bool() // uncache -> LSQ
-  
+
   def init: Unit = {
     valid := false.B
     inflight := false.B
@@ -148,12 +147,12 @@ class UncacheEntryState(implicit p: Parameters) extends DCacheBundle {
   def isWaitSame(): Bool = valid && waitSame
   def can2Bus(): Bool = valid && !inflight && !waitSame && !waitReturn
   def can2Lsq(): Bool = valid && waitReturn
-  
+
   def setValid(x: Bool): Unit = { valid := x}
   def setInflight(x: Bool): Unit = { inflight := x}
   def setWaitReturn(x: Bool): Unit = { waitReturn := x }
   def setWaitSame(x: Bool): Unit = { waitSame := x}
-  
+
   def updateUncacheResp(): Unit = {
     assert(inflight, "The request was not sent and a response was received")
     inflight := false.B
@@ -271,7 +270,7 @@ class UncacheImp(outer: Uncache)extends LazyModuleImp(outer)
 
   def canMergePrimary(x: UncacheWordReq, e: UncacheEntry): Bool = {
     // vaddr same, properties same
-    getBlockAddr(x.vaddr) === getBlockAddr(e.vaddr) && 
+    getBlockAddr(x.vaddr) === getBlockAddr(e.vaddr) &&
       x.cmd === e.cmd && x.nc && e.nc &&
       x.memBackTypeMM === e.memBackTypeMM && !x.atomic && !e.atomic &&
       continueAndAlign(x.mask | e.mask)
@@ -515,7 +514,7 @@ class UncacheImp(outer: Uncache)extends LazyModuleImp(outer)
     val (f1_fwdDataTmp, f1_fwdMaskTmp) = doMerge(f1_flyData, f1_flyMask, f1_idleData, f1_idleMask)
     val f1_fwdMask = shiftMaskToHigh(f1_fwdPAddr, f1_fwdMaskTmp).asTypeOf(Vec(VDataBytes, Bool()))
     val f1_fwdData = shiftDataToHigh(f1_fwdPAddr, f1_fwdDataTmp).asTypeOf(Vec(VDataBytes, UInt(8.W)))
-    // paddr match and mismatch judge 
+    // paddr match and mismatch judge
     val f1_ptagMatches = sizeMap(w => addrMatch(RegEnable(entries(w).addr, f0_fwdValid), f1_fwdPAddr))
     f1_tagMismatchVec(i) := sizeMap(w =>
       RegEnable(f0_vtagMatches(w), f0_fwdValid) =/= f1_ptagMatches(w) && RegEnable(f0_validMask(w), f0_fwdValid) && f1_fwdValid