timing(icache): remove tag-related clock gating for timing (OpenXiang…

…Shan#4246)
ZTHKaiYuan · Feb 7, 2025 · 981114e · 981114e
1 parent f5217f4
commit 981114e
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/xiangshan/frontend/icache/ICache.scala b/src/main/scala/xiangshan/frontend/icache/ICache.scala
@@ -271,7 +271,7 @@ class ICacheMetaArray(implicit p: Parameters) extends ICacheArray with HasICache
       shouldReset = true,
       holdRead = true,
       singlePort = true,
-      withClockGate = true
+      withClockGate = false // enable signal timing is bad, no gating here
     ))
 
     // meta connection
@@ -431,7 +431,7 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray with HasICache
         shouldReset = true,
         holdRead = true,
         singlePort = true,
-        withClockGate = false // enable signal timing is bad, no gating here
+        withClockGate = true
       ))
 
       // read