fix(LoadUnit): corrupt should be triggered on valid mshr (OpenXiangSh…

…an#4292)
ZTHKaiYuan · Feb 20, 2025 · 5a36f63 · 5a36f63
1 parent deb28c0
commit 5a36f63
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
@@ -1301,7 +1301,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule
   s2_real_exceptionVec(loadAddrMisaligned) := s2_out.isMisalign && s2_check_mmio
   s2_real_exceptionVec(loadAccessFault) := s2_exception_vec(loadAccessFault) ||
     s2_fwd_frm_d_chan && s2_d_corrupt ||
-    s2_fwd_frm_mshr && s2_mshr_corrupt
+    s2_fwd_data_valid && s2_fwd_frm_mshr && s2_mshr_corrupt
   val s2_real_exception = s2_vecActive &&
     (s2_trigger_debug_mode || ExceptionNO.selectByFu(s2_real_exceptionVec, LduCfg).asUInt.orR)