area(TagArray): split TagArray from 4way to 2way per array (OpenXia…

…ngShan#4287)
ZTHKaiYuan · Feb 19, 2025 · 2df9c39 · 2df9c39
1 parent ccd7d22
commit 2df9c39
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Showing 2 changed files with 33 additions and 8 deletions.
diff --git a/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala b/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
@@ -129,6 +129,7 @@ trait HasDCacheParameters extends HasL1CacheParameters with HasL1PrefetchSourceP
   // banked dcache support
   val DCacheSetDiv = 1
   val DCacheSets = cacheParams.nSets
+  val DCacheWayDiv = 2
   val DCacheWays = cacheParams.nWays
   val DCacheBanks = 8 // hardcoded
   val DCacheDupNum = 16

diff --git a/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala b/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
@@ -51,25 +51,29 @@ abstract class AbstractTagArray(implicit p: Parameters) extends DCacheModule {
   val TagEccParam = if(EnableTagEcc) Some(HasTagEccParam) else None
 }
 
-class TagArray(implicit p: Parameters) extends AbstractTagArray {
+class TagSRAMBank(index: Int)(implicit p: Parameters) extends AbstractTagArray {
   val io = IO(new Bundle() {
-    val read = Flipped(DecoupledIO(new TagReadReq))
-    val resp = Output(Vec(nWays, UInt(encTagBits.W)))
-    val write = Flipped(DecoupledIO(new TagWriteReq))
+    val read = Flipped(DecoupledIO(new TagReadReq {
+      override val way_en = UInt(DCacheWayDiv.W)
+    }))
+    val resp = Output(Vec(DCacheWayDiv, UInt(encTagBits.W)))
+    val write = Flipped(DecoupledIO(new TagWriteReq {
+      override val way_en = UInt(DCacheWayDiv.W)
+    }))
   })
   // TODO: reset is unnecessary?
   val rst_cnt = RegInit(0.U(log2Up(nSets + 1).W))
   val rst = rst_cnt < nSets.U
   val rstVal = 0.U
   val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
   val wdata = Mux(rst, rstVal, io.write.bits.asECCTag())
-  val wmask = Mux(rst || (nWays == 1).B, (-1).asSInt, io.write.bits.way_en.asSInt).asBools
-  val rmask = Mux(rst || (nWays == 1).B, (-1).asSInt, io.read.bits.way_en.asSInt).asBools
+  val wmask = Mux(rst || (DCacheWayDiv == 1).B, (-1).asSInt, io.write.bits.way_en.asSInt).asBools
+  val rmask = Mux(rst || (DCacheWayDiv == 1).B, (-1).asSInt, io.read.bits.way_en.asSInt).asBools
   when (rst) {
     rst_cnt := rst_cnt + 1.U
   }
 
-  val tag_array = Module(new SRAMTemplate(UInt(encTagBits.W), set = nSets, way = nWays,
+  val tag_array = Module(new SRAMTemplate(UInt(encTagBits.W), set = nSets, way = DCacheWayDiv,
     shouldReset = false, holdRead = false, singlePort = true, withClockGate = true))
 
   val wen = rst || io.write.valid
@@ -88,7 +92,27 @@ class TagArray(implicit p: Parameters) extends AbstractTagArray {
   tag_array.io.r.req.bits.apply(setIdx = io.read.bits.idx)
   io.resp := tag_array.io.r.resp.data
 
-  XSPerfAccumulate("part_tag_read_counter", tag_array.io.r.req.valid)
+  XSPerfAccumulate("part_tag_read_counter_" + index, tag_array.io.r.req.valid)
+}
+
+class TagArray(implicit p: Parameters) extends AbstractTagArray {
+  val io = IO(new Bundle() {
+    val read = Flipped(DecoupledIO(new TagReadReq))
+    val resp = Output(Vec(nWays, UInt(encTagBits.W)))
+    val write = Flipped(DecoupledIO(new TagWriteReq))
+  })
+
+  val tag_arrays = List.tabulate(nWays / DCacheWayDiv)(i => Module(new TagSRAMBank(i)))
+  tag_arrays.zipWithIndex.foreach { case (tag_array, i) =>
+    tag_array.io.read <> io.read
+    tag_array.io.read.bits.way_en := io.read.bits.way_en((i + 1) * DCacheWayDiv - 1, i * DCacheWayDiv)
+    tag_array.io.write <> io.write
+    tag_array.io.write.bits.way_en := io.write.bits.way_en((i + 1) * DCacheWayDiv - 1, i * DCacheWayDiv)
+  }
+  io.resp.zip(tag_arrays.map(_.io.resp).flatten).foreach {
+    case (resp, bank_resp) =>
+      resp := bank_resp
+  }
 }
 
 class DuplicatedTagArray(readPorts: Int)(implicit p: Parameters) extends AbstractTagArray {