Active ports encoding for PE

StanfordAHA · Jan 15, 2025 · c9440e5 · c9440e5
1 parent 8e69610
commit c9440e5
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/canal/interconnect.py b/canal/interconnect.py
@@ -544,7 +544,8 @@ def get_route_bitstream(self, routes: Dict[str, List[List[Node]]], use_fifo: boo
 
         return result
 
-    def configure_placement(self, x: int, y: int, instr, pnr_tag=None):
+    def configure_placement(self, x: int, y: int, instr, pnr_tag=None, node_num=None, active_core_ports=None):
+        instance_name = f"{pnr_tag}{node_num}"
         tile = self.tile_circuits[(x, y)]
         core_: ConfigurableCore = None
         result = None
@@ -563,7 +564,10 @@ def configure_placement(self, x: int, y: int, instr, pnr_tag=None):
                     tags = [tags]
                 for tag in tags:
                     if tag.tag_name == pnr_tag:
-                        result = core.get_config_bitstream(instr)
+                        if 'P' in pnr_tag or 'p' in pnr_tag:
+                            result = core.get_config_bitstream([instr, active_core_ports[instance_name]])
+                        else:
+                            result = core.get_config_bitstream(instr)
                         has_configured = True
                         core_ = core
                         break
@@ -825,3 +829,4 @@ def get_bit_widths(self):
 
     def name(self):
         return "Interconnect"
+