Skip to content

Commit

Permalink
Merge pull request #57 from StanfordAHA/regs-per-tile
Browse files Browse the repository at this point in the history
Added multi regs per tile
  • Loading branch information
jack-melchert authored Jun 5, 2023
2 parents 9fd0a87 + 840e166 commit 2d45854
Showing 1 changed file with 7 additions and 7 deletions.
14 changes: 7 additions & 7 deletions canal/interconnect.py
Original file line number Diff line number Diff line change
Expand Up @@ -647,9 +647,9 @@ def __dump_layout_file(self, layout_file, max_num_col):
for x in range(max_num_col):
coord = (x, y)
if coord not in self.tile_circuits:
f.write("1")
f.write("1 ")
else:
f.write("0")
f.write("0 ")
f.write("\n")
f.write("END\n")
# looping through the tiles to figure what core it has
Expand All @@ -667,15 +667,15 @@ def __dump_layout_file(self, layout_file, max_num_col):
for x in range(max_num_col):
coord = (x, y)
if coord not in self.tile_circuits:
f.write("0")
f.write("0 ")
else:
tile = self.tile_circuits[coord]
cores = [tile.core] + tile.additional_cores
core_names = [core.name() for core in cores]
if core_name not in core_names:
f.write("0")
f.write("0 ")
else:
f.write("1")
f.write("1 ")
f.write("\n")
f.write("END\n")
# handle registers
Expand All @@ -685,9 +685,9 @@ def __dump_layout_file(self, layout_file, max_num_col):
for y in range(self.y_max + 1):
for x in range(max_num_col):
if (x, y) in r_locs:
f.write("1")
f.write("20 ")
else:
f.write("0")
f.write("0 ")
f.write("\n")
f.write("END\n")

Expand Down

0 comments on commit 2d45854

Please sign in to comment.