Clean up

canal/circuit.py

@@ -1208,7 +1208,6 @@ def __lift_ports(self):
             if sb.switchbox.num_track > 0:
                 continue
             # lift the input ports up
-            #print(self.core)
             for bt, port_name in self.core_interface.inputs():
                 if bt != bit_width:
                     continue
@@ -1217,9 +1216,6 @@ def __lift_ports(self):
                 # if it has no connection, then we lift it up
                 port_node = self.tiles[bit_width].ports[port_name]
                 if port_node.get_conn_in():
-                    # print("\nConn in is true!")
-                    # print(port_node)
-                    # print("\n")
                     cb_input_port = self.cbs[port_name].ports.I
                     # use the CB input type instead
                     self.add_port(port_name, cb_input_port.base_type())
@@ -1231,15 +1227,9 @@ def __lift_ports(self):
                         p = self.add_port(port_name + "_valid", magma.BitIn)
                         self.safe_wire(p, self.cbs[port_name].ports.valid_in)
                 else:
-                    # print("\nConn in is false!")
-                    # print(port_node)
-                    # print("\n")
                     self.add_port(port_name, magma.In(magma.Bits[bit_width]))
                     self.wire(self.ports[port_name], self.core.ports[port_name])
                     if self.ready_valid and port_name not in self.combinational_ports:
-                        # if "flush" in port_name:
-                        #     continue 
-                        #    print(f"port name not in combo ports: {port_name}")
                         core_ready = self.core.ports[port_name + "_ready"]
                         core_valid = self.core.ports[port_name + "_valid"]
                         if core_valid.base_type() is magma.In(magma.Bits[1]):

canal/cyclone.py

@@ -482,11 +482,8 @@ def __add_core(self, core: InterconnectCore,
                    CoreConnectionType.Default):
         if connection_type & CoreConnectionType.CB == CoreConnectionType.CB:
             inputs = core.inputs()[:]
-            #print(inputs)
             inputs.sort(key=lambda x: x[1])
             for width, port_name in inputs:
-                #if "mu2io_16_1" in port_name:
-                #    breakpoint()
                 if width == self.track_width:
                     self.inputs.add(port_name)
                     # create node
@@ -501,8 +498,6 @@ def __add_core(self, core: InterconnectCore,
             outputs = core.outputs()[:]
             outputs.sort(key=lambda x: x[1])
             for width, port_name in outputs:
-                #if "io2f_17_0" in port_name:
-                #    breakpoint()
                 if width == self.track_width:
                     self.outputs.add(port_name)
                     # create node

canal/interconnect.py

@@ -86,8 +86,6 @@ def __init__(self, interconnects: Dict[int, InterconnectGraph],
                             double_buffer=self.double_buffer,
                             ready_valid=self.ready_valid)
 
-        #breakpoint()
-
         # we need to deal with inter-tile connections now
         # we only limit mesh
 
@@ -266,9 +264,6 @@ def __lift_ports(self):
                             self.wire(p, tile.ports[sb_name + "_ready"])
                             self.__interface[ready_name] = sb_port
 
-    # def connect_matrix_unit_stall_port(self):
-    #     breakpoint()
-
     def __connect_margin_tiles(self):
         # connect these margin tiles
         # margin tiles have empty switchbox
@@ -702,6 +697,8 @@ def parse_node(self, node_str):
         elif node_str[0] == "REG":
             reg_name, track, x, y, bit_width = node_str[1:]
             graph = self.get_graph(bit_width)
+            if reg_name not in graph.get_tile(x, y).switchbox.registers:
+                breakpoint()
             return graph.get_tile(x, y).switchbox.registers[reg_name]
         elif node_str[0] == "RMUX":
             rmux_name, x, y, bit_width = node_str[1:]

canal/util.py

@@ -37,14 +37,6 @@ def compute_num_tracks(x_offset: int, y_offset: int,
 
 
 def get_array_size(width, height, io_sides):
-    #x_min = 1 if io_sides & IOSide.West else 0
-
-    # MO: Temporary hack 
-    #x_min = 1
-    # x_max = width - 2 if io_sides & IOSide.East else width - 1
-    # y_min = 1 if io_sides & IOSide.North else 0
-    # y_max = height - 2 if io_sides & IOSide.South else height - 1
-
     x_min = 1 if IOSide.West in io_sides else 0
     x_max = width - 2 if IOSide.East in io_sides else width - 1
     y_min = 1 if IOSide.North in io_sides else 0
@@ -95,14 +87,12 @@ def create_uniform_interconnect(width: int,
 
     :return configured Interconnect object
     """
-    # if io_sides & IOSide.None_ or io_conn is None:
     if IOSide.None_ in io_sides or io_conn is None:
         io_conn = {"in": {}, "out": {}}
     tile_height = 1
     interconnect = InterconnectGraph(track_width)
     # based on the IO sides specified. these are inclusive
     # once it's assigned to None, nullify everything
-    # if io_sides & IOSide.None_:
     if IOSide.None_ in io_sides:
         io_sides = IOSide.None_
     x_min, x_max, y_min, y_max = get_array_size(width, height, io_sides)
@@ -143,37 +133,14 @@ def create_uniform_interconnect(width: int,
             if tile is not None:
                 continue
             core = column_core_fn(x, y)
-
-            #breakpoint()
-
-            # Here the MU ports are still alive
-            # if x == 0 and y == 7:
-            #     print(core.ports)
-
-            # They seem to disappear afterwards...figure out where they disappear and why
-            # Figure out how to alter the io_cons to include mu2f and vice versa 
 
             sb = SwitchBox(x, y, 0, track_width, [])
             tile_circuit = Tile(x, y, track_width, sb, tile_height)
-            interconnect.add_tile(tile_circuit)
-
+            interconnect.add_tile(tile_circuit)   
             core_interface = CoreInterface(core)
-            # if x == 0 and y == 7:
-            #     print(core_interface.inputs())
-            #     print(core_interface.outputs())
-                #breakpoint()
             interconnect.set_core(x, y, core_interface)
-            # if x == 0 and y == 7:
-            #     print(interconnect[(x, y)].inputs)
-            #     print(interconnect[(x, y)].outputs)
-                #breakpoint()
-
+
 
-    #print(interconnect[(0, 7)].ports)
-    # print(interconnect[(1, 0)].inputs)
-    # print(interconnect[(1, 0)].outputs)
-    # print(interconnect[(1, 0)].core)
-    #breakpoint()
     # set port connections
     port_names = list(port_connections.keys())
     port_names.sort()
@@ -200,7 +167,6 @@ def create_uniform_interconnect(width: int,
 
     # insert io
     connect_io(interconnect, io_conn["in"], io_conn["out"], io_sides)
-    #breakpoint()
 
     # insert pipeline register
     if pipeline_reg is None:
@@ -221,7 +187,6 @@ def connect_io(interconnect: InterconnectGraph,
                output_port_conn: Dict[str, List[int]],
                io_sides: List[IOSide]):
     """connect tiles on the side"""
-    # if io_sides & IOSide.None_:
     if IOSide.None_ in io_sides:
         return
 
@@ -237,7 +202,6 @@ def connect_io(interconnect: InterconnectGraph,
             # make sure that these margins tiles have empty switch boxes
             tile = interconnect[(x, y)]
 
-            # print(f"X: {x}, Y: {y}")
             if tile.core.core is None:
                 continue
             assert tile.switchbox.num_track == 0
@@ -269,9 +233,6 @@ def connect_io(interconnect: InterconnectGraph,
                                                        SwitchBoxIO.SB_OUT)
                             sb_node.add_edge(port_node)
 
-            # if "io2f_17_0" in output_port_conn:
-            #     print("Hit breakpoint")
-            #     breakpoint()
 
             for output_port, conn in output_port_conn.items():
                 # output is IO to fabric