A specialized ASIC to rapidly compute AES-128.
This repository conatins verilog code for a Custom Cryptographic module. When Synthesized, this ASIC is capable of encrypting data sent to it over an AHB-lite bus with AES-128. The device comes embedded with a Master Private Key that never leaves the ASIC. The MPK is used to encrypt the auxiliary key used to encrypt the data after the encryption is complete. This allows for the auxiliary key used in the encryption to be stored outside of the device and makes it so that this device is the only thing capable of decrypting the data.
Some of the build scripts and synthesis files for this project were written by Purdue University and are currently proprietary information. All functionality and design code for the processor is posted here and was written by myself and my team.
- Verilog/System Verilog - Used to generate the circuit layout.
- Ryan Devlin - Design and testing - RyanDevlin
- Dhairya Agrawal - Design and testings - DhairyaAgrawal
- Samuale Yigrem - Design and testing - SamualeYigrem
- Samanth Mottera - Design and testing - SamanthMottera
This project is licensed under the MIT License - see the LICENSE.md file for details
- Thanks to Dr. Mark Johnson for organizing this project.
- Thanks to Tim Prichett for technical guidance.
- Thanks to Reena Elangovan for technical guidance.