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1. 6TSRAM 6TSRAM Public

   Simulation files and documentation for the Energy-Efficient 6T SRAM Cell Design project, created for the Ratan Tata Tribute Circuit Design & Simulation Hackathon, focusing on a low-power 130nm SRAM…

   1

2. Digital_clk Digital_clk Public

   This repository contains data and code related to design of digital clock using verilog code.

   Verilog

3. Techademy_Dynamic-memory-allocation-in-C- Techademy_Dynamic-memory-allocation-in-C- Public

   C++

4. Digital_calender_using_verilog Digital_calender_using_verilog Public

   Verilog code for digital calender

   Verilog

5. 3bit_bus_arbiter 3bit_bus_arbiter Public

   Verilog code for 3 bit bus arbiter

   Verilog

6. 4bit_Rippercarryadder 4bit_Rippercarryadder Public

   verilod code for 4 bit ripple carry adder

   Verilog