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timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic #4254

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merged 1 commit into from
Feb 20, 2025

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@cz4e cz4e commented Feb 10, 2025

There is no exception misaligned store instruction enters the misalignbuffer. Due to the exception timing difference generated by the PMA, the timing of the misalignbuffer rejection condition is bad timing, which in turn leads to the bad timing of feedback_slow.hit.

There is no exception misaligned store instruction  enters the misalignbuffer.
Due to the exception timing difference generated by the PMA, the timing of the
misalignbuffer rejection condition is bad timing, which in turn leads to the
poor timing of feedback_slow.hit.
@cz4e cz4e added the timing Fix bad timing label Feb 10, 2025
@cz4e cz4e requested a review from Anzooooo February 10, 2025 02:43
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[Generated by IPC robot]
commit: 015b48c

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
015b48c 1.819 0.442 2.634 1.224 2.144 1.498 2.145 2.359 0.943 1.388 1.998 3.101 2.555 2.272 3.300

master branch:

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
4b9ddb8 0.442 2.634 1.235 2.144 1.498 2.145 2.359 0.943 1.380 1.998 3.101 2.555 2.272 3.300
4aeb0b1 2.634 2.359 1.380
9e12e8e 1.819 0.442 2.634 1.241 2.144 1.498 2.145 2.359 0.943 1.388 1.998 3.101 2.555 2.272 3.300
5f84a7f 1.819 0.442 2.634 1.236 2.144 1.498 2.145 2.359 0.943 1.380 1.998 3.101 2.555 2.272 3.300
c590fb3 1.819 0.442 2.634 1.233 2.144 1.498 2.145 2.359 0.943 1.388 1.998 3.101 2.555 2.272 3.300
981114e 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.359 0.943 1.380 1.998 3.101 2.555 2.272 3.300
f5217f4 1.819 0.442 2.634 1.235 2.144 1.498 2.145 2.359 0.943 1.380 1.998 3.101 2.555 2.272 3.300
977ac3b 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.359 0.943 1.388 1.998 3.101 2.555 2.272 3.300
75efee3 1.819 0.442 2.634 1.223 2.144 1.498 2.145 2.359 0.943 1.388 1.998 3.101 2.555 2.272 3.300

@linjuanZ linjuanZ changed the title timing(StoreUnit, StoreMisalignBuffer): adjust misalign buffer enq logic timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic Feb 20, 2025
@linjuanZ linjuanZ merged commit a94ed9a into master Feb 20, 2025
10 checks passed
@linjuanZ linjuanZ deleted the timing-misalign-enq branch February 20, 2025 02:58
ChrisYzcc pushed a commit to ChrisYzcc/XiangShan that referenced this pull request Feb 22, 2025
…penXiangShan#4254)

There is no exception misaligned store instruction enters the
misalignbuffer. Due to the exception timing difference generated by the
`PMA`, the timing of the misalignbuffer rejection condition is bad
timing, which in turn leads to the bad timing of `feedback_slow.hit`.
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3 participants