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70004 & 70046: added friday ADSD lecture and advanced security
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## Definition | ||
Being able to determine the attacker or [[Principle]]. | ||
- Audit trails and logs, even in security failure there is a need to detect in order to react, and investigate after is system is re-secured. | ||
- Secure timestamping (e.g. using OS, or network, attacker may attempt to damage integrity of logs) |
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## Definition | ||
The uptime of a system. | ||
- Maximum traffic, measured historically and guaranteed by SLAs with providers. | ||
- Using redundancy to reduce possible single points of failure (e.g. replicating databases, auto-scaling for load) | ||
Many attacks are [[Denial of Service]]. |
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## Definition | ||
Using multiple layers of security, and monitoring to remove single points of failure for security. | ||
## Example | ||
### Account monitoring | ||
- Using password authentication for accounts. | ||
- Monitor number of denied logins, conservatively blocking clients that fail to log in repeatedly. | ||
- Monitor logins for suspicious activity, and block judiciously. | ||
- Monitor suspected compromised accounts. |
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## Definition | ||
Overwhelming public services with large volumes of illegitimate traffic to prevent them servicing legitimate traffic. |
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## Definition | ||
> *Alice wants to prove to Trent she did communicate with Bob* | ||
Collecting undeniable evidence of some transaction. | ||
- receipts, digitally signed logs | ||
- helps with [[Accountability]], and for investigations (e.g. determining if a transaction was fraudulent, or valid based on an untrusted customer's testimony). |
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## Definition | ||
Rather than using the CPU to transfer data from main memory to a peripheral (wastes cycles), a separate DMA module does this (needs to update cache also). | ||
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*Note: Here we reference main memory but this could apply to any bus connected perhipheral or cache.* | ||
## Modes | ||
| Mode | Description | Speed | | ||
| ---- | ---- | ---- | | ||
| Burst | DMA gains access to system bus and releases it on task completion | Fastest | | ||
| Cycle Stealing | DMA forces CPU to release bus, makes small transfer. Repeats until task is complete. | Slow | | ||
| Transparent/Interleaving | DMA only takes control of the bus when the CPU does not need it. | Slowest | |
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## Definition | ||
*From the paper: [Roofline: an insightful visual performance model for multicore architectures: Communications of the ACM: Vol 52, No 4](https://dl.acm.org/doi/10.1145/1498765.1498785)* | ||
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![[roofile_model.drawio.svg]] | ||
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For example the original paper compare floating point arithmetic performance, and memory bandwidth. | ||
- We graph the attainable performance (i.e. $flops/s$ ) against the operational intensity (i.e. $flops/byte$). | ||
- The gradient is $bytes/s$ (the memory bandwidth) | ||
- We get an increase up to a point (where $flops/s$ remains constant and it is compute bound) |
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70046 - Advanced Digital Systems Design/roofile_model.drawio.svg
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