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Designing, implementing and testing a Harvard, RISC-like, five-stages pipeline processor.

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ALU_test.v
ALU_test.v
 
 
ALU_test.v.out
ALU_test.v.out
 
 
DataMemory.txt
DataMemory.txt
 
 
InstructionMemory.txt
InstructionMemory.txt
 
 
Interface.txt
Interface.txt
 
 
README.md
README.md
 
 
Tasks_Implementation.txt
Tasks_Implementation.txt
 
 
TestCase.txt
TestCase.txt
 
 
alu_16bit.v
alu_16bit.v
 
 
alu_16bit.v.out
alu_16bit.v.out
 
 
alu_control_unit.v
alu_control_unit.v
 
 
alu_control_unit.v.out
alu_control_unit.v.out
 
 
alu_control_unit_test.v
alu_control_unit_test.v
 
 
append_zeros.v
append_zeros.v
 
 
assembler.py
assembler.py
 
 
buffer.v
buffer.v
 
 
call_control.v
call_control.v
 
 
call_control.v.out
call_control.v.out
 
 
call_control_test.v
call_control_test.v
 
 
call_control_test.v.out
call_control_test.v.out
 
 
control_unit.v
control_unit.v
 
 
control_unit.v.out
control_unit.v.out
 
 
control_unit_test.v
control_unit_test.v
 
 
data_memory.v
data_memory.v
 
 
decode_stage.v
decode_stage.v
 
 
decoder_3x8.v
decoder_3x8.v
 
 
decoder_3x8_test.v
decoder_3x8_test.v
 
 
execute_stage.v
execute_stage.v
 
 
execute_stage.v.out
execute_stage.v.out
 
 
fetch_stage.v
fetch_stage.v
 
 
forwarding_unit.v
forwarding_unit.v
 
 
forwarding_unit.v.out
forwarding_unit.v.out
 
 
forwarding_unit_test.v
forwarding_unit_test.v
 
 
forwarding_unit_test.v.out
forwarding_unit_test.v.out
 
 
handle_jumps.v
handle_jumps.v
 
 
handle_jumps_test.v
handle_jumps_test.v
 
 
handle_jumps_test.v.out
handle_jumps_test.v.out
 
 
immediate_control.v
immediate_control.v
 
 
immediate_control_test.v
immediate_control_test.v
 
 
includes.v
includes.v
 
 
instruction_memory.v
instruction_memory.v
 
 
interput_control.v.out
interput_control.v.out
 
 
interput_control_test.v.out
interput_control_test.v.out
 
 
interupt_contol.v.out
interupt_contol.v.out
 
 
interupt_control.v
interupt_control.v
 
 
interupt_control.v.out
interupt_control.v.out
 
 
interupt_control_test.v
interupt_control_test.v
 
 
interupt_control_test.v.out
interupt_control_test.v.out
 
 
load_use_case.v
load_use_case.v
 
 
load_use_case.v.out
load_use_case.v.out
 
 
load_use_case_test.v
load_use_case_test.v
 
 
load_use_case_test.v.out
load_use_case_test.v.out
 
 
lol.txt
lol.txt
 
 
mad_risc_processor.v
mad_risc_processor.v
 
 
mad_risc_processor.v.out
mad_risc_processor.v.out
 
 
mad_risc_processor_test.v
mad_risc_processor_test.v
 
 
memory_stage.v
memory_stage.v
 
 
memory_stage_test.v
memory_stage_test.v
 
 
mux_2x1_16bit.v
mux_2x1_16bit.v
 
 
mux_2x1_16bit_test.v
mux_2x1_16bit_test.v
 
 
mux_2x1_1bit.v
mux_2x1_1bit.v
 
 
mux_2x1_32bit.v
mux_2x1_32bit.v
 
 
mux_8x3_1bit.v
mux_8x3_1bit.v
 
 
mux_8x3_1bit_test.v
mux_8x3_1bit_test.v
 
 
myFile.txt
myFile.txt
 
 
new.txt
new.txt
 
 
personalNote.txt
personalNote.txt
 
 
register_16bit.v
register_16bit.v
 
 
register_16bit_f.v
register_16bit_f.v
 
 
register_32bit_PC.v
register_32bit_PC.v
 
 
register_32bit_PC.v.out
register_32bit_PC.v.out
 
 
register_32bit_PC_test.v
register_32bit_PC_test.v
 
 
register_32bit_SP.v
register_32bit_SP.v
 
 
register_file.v
register_file.v
 
 
register_generic.v
register_generic.v
 
 
register_generic.v.out
register_generic.v.out
 
 
select_wb_value.v
select_wb_value.v
 
 
severeJumpCase.txt
severeJumpCase.txt
 
 
shift_left_by_two.v
shift_left_by_two.v
 
 
shift_left_by_two_test.v
shift_left_by_two_test.v
 
 
sign_extend.v
sign_extend.v
 
 
sign_extend_test.v
sign_extend_test.v
 
 
sp_alu_32bit.v
sp_alu_32bit.v
 
 
sp_module.v
sp_module.v
 
 
timingDiagram.txt
timingDiagram.txt
 
 
transcript
transcript
 
 
writeback_stage.v
writeback_stage.v
 
 

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MAD_RISC-processor

A RISC-like, five-stage pipelined processor.

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Designing, implementing and testing a Harvard, RISC-like, five-stages pipeline processor.

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