An emulated PC with a RISC II processor. See this page for an in-depth description of the RISC II processor.
The RISC II was an experimental processor created at UC Berkeley by Manolis Katevenis and Robert Sherburne under professors David Patterson and Carlo Séquin. It was completed in 1983 as the successor to the original RISC processor. It had a simple design with 32 bit instructions, only two instruction formats, and only two addressing modes. The RISC II served as the primary inspiration for the Sun SPARC architecture, an early industry implementation of RISC.
Documentation on the RISC II is scarce and its technical details can only be found in Katevenis’ PhD thesis. This project exists to preserve knowledge on this important piece of computer history.
See this project for an experimental assembler for the RISC II.
This emulator contains a debugging tool that shows the inner workings of the CPU’s data path.
A screenshot of the debugger:
| Feature | State |
|---|---|
| RISC II instruction set emulation | Partial (Incomplete and with bugs) |
| Screen output & I/O | Work started |
| MMU/Virtual Memory | No |
| Firmware | No |