MIPT-MIPS 2018
Micro-architectural precision:
- Fetching unit incorporating Instruction cache by Aleksandr Misevich
- Data bypasses and complex pipeline by Denis Los
Support of more MIPS instructions:
- Multiplication and division instructions:
- MIPS I:
mult,multu,div,divu,mfhi,mflo,mthi,mtloby Pavel Kryukov - MIPS32:
mulby Pavel Kryukov
- MIPS I:
- Accumulating multiplication of MIPS32 by Andrei Sultan:
madd,maddu,msub,msubu - Unaligned memory accesses by Andrei Sultan:
lwl,lwr,swl,swr - Linked loads/conditional stores without atomicity warranties by Pavel Kryukov:
ll,sc
MIPS64 infrastructure and experimental implementation of instructions by Kirill Nedostoev, Alexander Timofeev, and Pavel Kryukov
- Doubleword arithmetics (MIPS III):
dadd,daddiu,daddu,dsub,dsubu - Doubleword shifts (MIPS III):
dsll,dsll32,dsra,dsra32,dsrl,dsrl32 - Doubleword variable shifts (MIPS III):
dsllv,dsrav,dsrlv - Doubleword memory accesses (MIPS III):
ld,lwu,sd,lld,scd - Doubleword multiplication/division (MIPS III):
ddiv,ddivu,dmult,dmultu - Doubleword count leading zeroes/ones (MIPS64):
dclo,dclz
RISC-V preparations by Aleksandr Misevich:
- Generalized infrastructure to support several ISA
- Placeholder for RISC-V implementation
- Implementation of RISC-V register file
Quality Assurance:
- CMake build and testing flow by Konstantin Soshin
- Unit tests for Register and Register File classes by Aleksandr Misevich
- Strict timing primitives by Denis Los
- Wrong code detector by Pavel Kryukov
Simulation speed improvements:
- Cached instruction integration to performance simulation by Pavel Kryukov
New manuals:
- „CMake“ by Konstantin Soshin
- „Introduction to TDD“ by Pavel Kryukov and Aleksandr Misevich
External PRs:
- AppVeyor: appveyor/ci#2096, appveyor/ci#2154
- EduMIPS64: EduMIPS64/edumips64#177
- LLVM: 36283, 36284, 36961, 36963
- Visual Studio: 225040